Spansion Llc.

Globalfoundries Inc.

Advanced Micro Devices Corporation

Cypress Semiconductor Corporation

Vidyut Gopal

David H Matsumoto

Jean Y Yang

Shankar Sinha

Jean Yee-Mei Yang

Phillip Lawrence Jones

Michael Brennan

In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Dielectric extension to mitigate short channel effects

A method of planarizing a semiconductor device is provided. The semiconductor device includes a substrate, first and second components provided on the surface of the substrate, and a first material provided between and above the first and second components. The first component has a height greater than a height of the second component. The method includes performing a first polishing step on the semiconductor device to remove the first material above a top surface of the first component, to remove the first material above a top surface of the second component, and to level the top surface of the first component. The method also includes performing a second polishing step on the semiconductor device to planarize the top surfaces of the first and second components.

Planarization method using hybrid oxide and polysilicon CMP

A method for forming a semiconductor device may include forming a silicon oxynitride mask layer over a first layer. The first layer may be etched using the silicon oxynitride mask layer, to form a pattern in the first layer. The pattern may be filled with a dielectric material. The dielectric material may be planarized using a ceria-based slurry and using the silicon oxynitride mask layer as a stop layer.

Method for improved planarization in semiconductor devices

Growing community of inventors

Saratoga, CA, United States of America

Vidyut Gopal