Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Pure Storage, Inc.

Rambus Inc.

Sandisk Enterprise IP LLC

Vidyabhushan Mohan

Jack Frayer

Robert W Ellis

Gordon James Coleman

Damian Pablo Yurzola

Melissa Kimble

Hari Kannan

Pankaj Mehra

Jay Sarkar

Cory J Peterson

Yao Zhang

Amir Sanayei

Hongzhong Zheng

Chang Hua Siau

Dejan Vucinic

Aaron Keith Olbrich

Grishma Shah

James M Higgins

Minghai Qin

Chao Sun

Seung-Hwan Song

Gopinath Balakrishnan

Arup De

Todd Lindberg

Joseph James Tringali

An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.

Acquiring failure information

Failure information associated with a plurality of blocks of a solid-state storage device of a plurality of solid-state storage devices is received. One or more blocks of the plurality of blocks storing uncorrectable data are identified based on the received failure information. A partial deallocation of the one or more blocks of the plurality of blocks is issued, the partial deallocation indicating that the one or more blocks store uncorrectable data. A remedial action associated with the one or more blocks of the plurality of blocks is performed.

Deallocation within a storage system

Online failure span determination

Systems and methods for solid-state storage drive-level failure prediction and health metric are described. A plurality of host-write commands are received at a solid-state storage device. A number of drive-writes per day based on the on the plurality of host-write commands is determined. An aggregated amount of degradation to one or more internal non-volatile memory components based on the number of drive-writes per day is determined. Using a machine-learned model, a probability of failure value based on a set of parameter data and the aggregated amount of degradation to the non-volatile memory component is generated. An alert is generated, based on the probability of failure value or degradation threshold.

Method and system involving degradation of non-volatile memory based on write commands and drive-writes

Data resiliency by partially deallocating data blocks of a storage device

Method and system for a storage (SSD) drive-level failure and health prediction leveraging machine learning on internal parametric data

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die, a local memory connected to (or part of) the controller and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations. When the memory system receives instructions to use the compute engine to perform data manipulation operations, the local memory is reallocated such that an amount of space allocated in the local memory for logical to physical translation information is changed based on the one or more data manipulation instructions.

Non-volatile storage system with integrated compute engine and optimized use of local fast memory

A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Non-volatile storage system with compute engine to accelerate big data applications

Systems and methods for increasing performance and reducing power consumption of a non-volatile memory system while the system acquires status information from a plurality of memory die are described. The non-volatile memory system may include a plurality of memory die and a system controller for controlling operations performed by each memory die of the plurality of memory die (e.g., read operations, write operations, or erase operations). The system controller may transmit or broadcast a first status command to each memory die of the plurality of memory die and in response simultaneously or concurrently receive one or more sets of status information from each memory die of the plurality of memory die. The status information may include ready/busy status information (e.g., indicating that a memory die is able to receive new data), programming loop count information, and erase loop count information.

Multi-die rolling status mode for non-volatile storage

Systems, methods, and/or devices are used to automate read operations performed at an open erase block. In one aspect, the method includes: receiving a read command, at a storage device, to read data from non-volatile memory of the storage device. In response to receiving the read command, the method further includes: 1) reading data using a first set of memory operation parameters in response to a determination that the read command is not for reading data from a predefined portion of an open erase block (e.g., an erase block that is determined to be an open erase block) of the non-volatile memory and 2) reading data using a second set of memory operation parameters (i.e., the second set is distinct from the first set) in response to a determination that the read command is for reading data from the predefined portion of an open erase block of the non-volatile memory.

Open erase block read automation

Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

High-priority NAND operations management

The various embodiments described herein include systems, methods and/or devices used to enable physical-to-physical address remapping in a storage module. In one aspect, the method includes, for each of a sequence of two or more units of non-volatile memory, determining a validity state of a respective unit of memory. In accordance with a determination that the validity state of the respective unit of memory is an invalid state, the method includes storing, in a table, a second address assigned to the respective unit of memory. At least a portion of the second address is a physical address portion corresponding to a physical location of a second unit of memory. In accordance with a determination that the validity state of the respective unit of memory is a valid state, the method includes forgoing assignment of the second address corresponding to the unit of memory.

Non-volatile memory module with physical-to-physical address remapping

The various embodiments described herein include systems, methods and/or devices used to package non-volatile memory. In one aspect, the method includes: (1) selecting, from a set of non-volatile memory die, a plurality of non-volatile memory die on which one or more tests have been deferred until after packaging, the selecting in accordance with wafer positions of the plurality of non-volatile memory die and statistical die performance information corresponding to the wafer positions; and (2) packaging the selected plurality of non-volatile memory die. In some embodiments, after said packaging, the method further includes performing a set of tests on the plurality of non-volatile memory die to identify respective units of memory within the plurality of non-volatile memory die that meet predefined validity criteria, wherein the set of tests performed include at least one of the deferred one or more tests.

Low-test memory stack for non-volatile storage

A memory address and a virtual cache identifier are received in association with a request to retrieve data from a cache data array. Context information is selected based on the virtual cache identifier, the context information indicating a first region of a plurality of regions within the cache data array. A cache line address that includes a first number of bits of the memory address in accordance with a size of the first region is generated and, if the cache data array is determined to contain, in a location indicated by the cache line address, a cache line corresponding to the memory address, the cache line is retrieved from the location indicated by the cache line address.

Virtualized cache memory

The embodiments described herein are used to execute staggered memory operations. The method includes, at each of a plurality of distinct memory portions of the storage device, establishing a non-zero command delay parameter distinct from a command delay parameter established for one or more of the other memory portions in the plurality of distinct memory portions. The method further includes, after establishing the non-zero command delay parameter in each of the plurality of distinct memory portions of the storage device, executing memory operations in two or more of the plurality of distinct memory portions of the storage device during overlapping time periods, the executing including, in each memory portion of the plurality of memory portions, delaying execution of a respective memory operation by an amount of time corresponding to the command delay parameter established for that memory portion.

Growing community of inventors

San Jose, CA, United States of America

Vidyabhushan Mohan