Mips Technologies, Inc.

Rivian IP Holdings, LLC

Arm Finance Overseas Limited

Vidya Rajagopalan

Radhika Thekkath

Karagada Ramarao Kishore

Franz Treue

Era Kasturia Nangia

Meng-Bing Yu

Michael Ni

Kevin D Kissell

G Michael Uhler

Lawrence Henry Hudepohl

Kjeld Svendsen

Xing Yu Jiang

Maria Ukanwa

David A Courtright

Søren Kragh

George Michael Uhler

Elaine Wenying Jin

Adel M Alsaadi

Systems and methods to enhance vehicle object detection capability are provided. The vehicle may include a first sensor coupled with a body of the vehicle, the first sensor having a first field of view and the first sensor comprising a polarizer. The vehicle may include a second sensor coupled with the body of the vehicle, the second sensor having a second field of view. The first field of view and the second field of view can at least partially overlap. The vehicle may include a processor coupled with memory. The processor can receive a first image captured by the first sensor and a second image captured by the second sensor. The processor can determine a luminance of light ratio associated with the first image and the second image, and can modify an image processing technique.

Heterogeneous on-vehicle camera system for object detection

A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.

Data cache virtual hint way prediction, and applications thereof

A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand that is both a source and a destination. If the value of the second operand is not equal to a specified value, the first decoded instruction moves the third operand to a completion buffer register. If the value of the second operand is equal to the specified value, the second decoded instruction moves the value of the first operand to the completion buffer. When the decoded instruction that performed the move graduates, the contents of the completion buffer register is transferred to a register file register specified by the third operand.

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.

Processor core and method for managing branch misprediction in an out-of-order processor pipeline

A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

System and method to trace high performance multi-issue processors

A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

Program counter and data tracing from a multi-issue processor

A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and tracking out-of-order transactions on either or both of the address or data portions of the computing bus. The bus interface includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the computing bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available. Snoop control logic is also provided to insure coherency between multiple instances of data within devices attached to the split transaction bus. Data release logic drives a data release signal on the last cycle of a data transaction to reduce latency between sequential data transactions by one or more masters on the computing bus.

Low latency system bus interface for multi-master processing environments

An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communication via a bus interface that includes split transaction tracking and control to establish transaction ID's for each transaction initiated by the bus interface, and to determine whether data appearing on the data portion of the system bus is associated with one of its pending transactions. The bus interface also contains flow control logic to determine whether devices that are to be read from, or written to, by the bus interface, have resources (buffers) available to respond to the transactions. If the resources are available, the flow control logic allows the transactions to proceed, and adjusts its counters to reflect the use of the resources. If the resources are not available, the flow control logic causes the transactions to wait until the resources become available.

Growing community of inventors

Palo Alto, CA, United States of America

Vidya Rajagopalan