Xilinx, Inc.

Vidya Gopalakrishnan

Christopher Y Karman

Anup Ganesh

Chih-Heng Tzang

Ramesh Barukula

A disclosed circuit arrangement includes a bus interface circuit and a configuration storage circuit coupled to the bus interface circuit. The bus interface circuit stores first error data in the configuration storage circuit in response to detection of an error condition. A second storage circuit provides storage of data, and an error re-logging circuit is coupled to the configuration storage circuit and to the second storage circuit. The error re-logging circuit polls the configuration storage circuit for the first error data signaling detection of an error, and in response to the first error data signaling detection of an error, stores the first error data in the second storage circuit, and clears the first error data from the configuration storage circuit to remove the signaling of the detection of the error.

Error re-logging in electronic systems

Some examples described herein provide for dynamically reconfiguring a base address register (BAR) of a Peripheral Component Interconnect Express (PCIe) configuration space. In an example, information relating to a BAR of a PCIe configuration space is written to a PCIe extended configuration space of the PCIe configuration space, which is read, by a dynamic BAR module. Respective values are written, by the dynamic BAR module, to bits of the BAR based on the information. After writing by the dynamic BAR module, a set value is attempted to be written to each of address bits of the BAR. Writing the set value to an address bit of the BAR is prevented when the address bit is set to a predefined value. After attempting to write, a read value is read from the bits of the BAR. A base address of memory is written to the BAR based on the read value.

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San Jose, CA, United States of America

Vidya Gopalakrishnan