Rambus Inc.

Vidhya Thyagarajan

Liji Gopalakrishnan

Sudhir Shetty

Gidda Reddy Gangula

Prasanna Kole

Methods and apparatuses that relate to an integrated circuit (IC) with adaptive power state management are described. The IC can be coupled with, and can control the operation of, a memory device. The IC and the memory device can be operated in multiple operational states, wherein each operational state may represent a tradeoff point between performance and power consumption. The IC may be capable of: (1) changing the operational state of the IC and/or the operational state of the memory device based on the occurrence of one or more conditions, and/or (2) changing the one or more conditions based on measuring one or more performance values associated with the IC and/or the memory device.

Integrated circuit with adaptive power state management

Memory controller concepts are disclosed in which hardware resources of a memory controller can be re-used or re-configured to accommodate various different memory configurations. The memory configuration may be stored in mode register bits (), settable by a host or operating system. By re-configuring or reallocating certain resources of a memory controller, for example command logic blocks (A, B, C, D in FIG.A), a single controller design can be used to interface efficiently with a variety of different memory components. Command logic blocks that support N&#xd7;M memory ranks, for example, can be reconfigured to support N ranks and M threads for multi-threaded memories (FIG.A). Data buffer () depth can be extended by reconfiguring the buffers responsive to the mode register bits (). Request buffers can be shared across command logic blocks, for example to increase the request buffer depth (FIG.A). Unused circuits can be powered down to save power consumption (FIG.A).

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Bengaluru, India

Vidhya Thyagarajan