International Business Machines Corporation

Apple Inc.

Qualcomm Incorporated

Vidhya Ramachandran

Jun Zhai

Shiqun Gu

Kunzhong Hu

Zhong-Xiang He

Sanjay Dabral

Chonghua Zhong

Douglas Duane Coolbaugh

Mengzhi Pang

Lawrence Alfred Clevenger

Shawn Searles

Ebenezer E Eshun

Subramanian Srikanteswara Iyer

Herbert Lei Ho

Kwan-Yu Lai

Joseph T DiBene, Ii

Barbara Ann Waterhouse

Chih-Chao Yang

Carl John Radens

Louis L Hsu

Keith Kwong Hon Wong

Timothy Joseph Dalton

Kevin Shawn Petrarca

Kaushik Arun Kumar

Stephan Grunow

David A Secker

Bradley Alan Orner

Ralf M Schmitt

Wenjie Mao

Jung Pill Kim

Wagdi William Abadeer

William Joseph Murphy

Michael Joseph Zierak

Natalie Barbara Feilchenfeld

Taehyun Kim

Dong Wook Kim

Chiew-Guan Tan

Brian Matthew Henderson

Eric Adler

Matthew D Moon

Rongtian Zhang

Michael Lawrence Gautsch

SivaChandra Jangam

Kangguo Cheng

Jeffrey P Gambino

Theodorus E Standaert

Seung Hyuk Kang

Shom Ponoth

Ping-Chuan Wang

Alvin Jose Joseph

Robert Mark Rassel

Choh Fei Yeap

Johnathan E Faltermeier

Ravindra Vaman Shenoy

Anil Kumar Chinthakindi

Jeffrey Xu

John Jianhong Zhu

Yu Lu

Stephen Arthur St Onge

Jon Lasiter

Rohan U Mandrekar

Jun Chen

Urmi Ray

Huabo Chen

Jihong Choi

Christine Sung-An Hau-Riege

Miguel Miranda Corbalan

Young Doo Jeon

Long Huang

Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

Wafer reconstitution and die-stitching

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

Structure and method for sealing a silicon IC

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

Structure and method for fabricating a computing system with an integrated voltage regulator module

Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

Power management system switched capacitor voltage regulator with integrated passive device

Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.

Trimmable banked capacitor

A system that includes multiple integrated circuits is disclosed. A first integrated circuit of the system includes a plurality of circuit blocks, and a first circuit block of the plurality of circuit blocks includes a first power terminal. A second integrated circuit of the system includes multiple voltage regulation circuits, a second power terminal coupled to an output of a given voltage regulation circuit, and a third power terminal coupled to an input of the given voltage regulation circuit. A substrate, included in the system, includes a plurality of conductive paths, each of which includes a plurality of wires fabricated on a plurality of conductive layers. The system further includes a power management unit that may be configured to generate a power supply voltage at a fourth power terminal that is coupled to the third power terminal via a first conductive path of the plurality of conductive paths.

Integrated passive devices to reduce power supply voltage droop

In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Dual-sided silicon integrated passive devices

Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps.

Systems and methods to reduce parasitic capacitance

Growing community of inventors

Ossining, NY, United States of America

Vidhya Ramachandran