National Semiconductor Corporation

Massachusetts Institute of Technology

Vida Ilderem

Alan G Solheim

Rick C Jerome

Ali A Iranmanesh

Christopher S Blair

Madan Biswal

Rajeeva Lahri

L Rafael Reif

Prabha K Tedrow

Steven M Leibiger

George E Ganschow

Bamdad Bastani

Bancherd DeLong

James L Bouknight

Steve M Leibiger

Tad Davies

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabricating BiCMOS device

A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits higher packing density, and lowers buried layer-to-substrate capacitance.

BiCMOS device having self-aligned well tap and method of fabrication

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for submicron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

High performance semiconductor devices and their manufacture

A method for formation of silicide structures on a semiconductor device. Oxide sidewalls are formed upon and selectively removed from polysilicon contacts. Refractory metal is deposited and heated, unreacted metal is removed, leaving a metal silicide on selected polysilicon sidewalls.

Formation of silicide contacts using a sidewall oxide process

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Reducing base resistance of a BJT by forming a self aligned silicide in

A BiCMOS device is revealed. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Interconnect method for semiconductor devices

A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits hgher packing density, and lowers buried layer-to-substrate capacitance.

The selective or blanket deposition of titanium silicide using a Very Low Pressure Chemical Vapor Deposition process is described. Silane and titanium tetrachloride are used as the silicon and titanium sources, respectively. A thin polysilicon layer is deposited prior to the silicide deposition to promote the nucleation of titanium silicide. It is shown that selective deposition is possible by controlling the polysilicon and the titanium silicide deposition times. The resulting titanium silicide films have resistivities in the range of 15-25 micro-ohms-cm.

Very low pressure chemical vapor deposition process for deposition of

This invention relates to a process and apparatus for the Low Pressure Chemical Vapor Deposition (LPCVD) of polycrystalline refractory metal silicides, such as TiSi.sub.2, in a reactor. An oxidized Si wafer is loaded in the reactor. The reactor is pumped down to a pressure of about 10.sup.-7 Torr, or less. The Si substrate is heated to the predetermined deposition temperature of about 630.degree. C. while avoiding heating of the reactor walls. The reactor is then purged with an inert gas, such as nitrogen. Next, polysilicon is deposited on the wafer by introducing SiH.sub.4 into the reactor at a pressure in the order of 0.2 Torr. A layer of polycrystalline titanium silicide is then formed on the polysilicon layer by introducing reactants, such as TiCl.sub.4 and SiH.sub.4, into the reactor at depositon temperatures between about 650.degree. to 700.degree. C. and pressures of between about 50 to 460 m Torr.

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Puyallup, WA, United States of America

Vida Ilderem