Motorola Corporation

Intel Corporation

Vida Ilderem Burger

Michael H Kaneshiro

Debabani Choudhury

Bryce D Horine

Jay Paul John

James Albert Kirchgessner

John W Steele

Diann M Dow

Richard W Mauntel

Shuhei Yamada

Michael P Masquelier

E James Prendergast

David L Stolfa

Rainer Thoma

Ik-Sung Lim

Kevin M Klein

Carl Kyono

Francis K Chai

Phillip W Dahl

Sharanda L Bigelow

Various antennas elements including antennas arrays can support various communication technologies and can be integrated into different components or subcomponents of a vehicle, including various vehicle light assemblies. The vehicular antennas elements include low profile and/or concealed antenna elements that are inconspicuous aesthetically and do not affect or substantially affect vehicle aerodynamics.

Embedded antennas structures for wireless communications and radar

A lateral PNP is disclosed in which a substrate of a first conductivity type is used. On top of the substrate a buried region of a second conductivity type is formed. A lightly doped collector region is located above the buried region. The lateral PNP also includes a base region of a second conductivity type formed by a graded channel implant and a well region of a second conductivity type, the well region contacting the base region, the buried region and a base contact. Additionally, there are collector contacts and emitter contacts of a first conductivity type. The lightly doped collector region results in a large Early voltage and the base region provides for a high current gain.

Lateral PNP and method of manufacture

A method of manufacturing a heterojunction BiCMOS IC. ( ) includes forming a gate electrode ( ), forming a protective layer ( ) over the gate electrode, forming a semiconductor layer ( ) over the protective layer, depositing an electrically insulative layer ( ) over the semiconductor layer, using a mask layer ( ) to define a doped region ( ) in the semiconductor layer and to define a hole ( ) in the electrically insulative layer, forming an electrically conductive layer ( ) over the electrically insulative layer, using another mask layer ( ) to define an emitter region ( ) in the electrically conductive layer and to define an intrinsic base region ( ) and a portion of an extrinsic base region ( ) in the electrically conductive layer, and using yet another mask layer ( ) to define another portion of the extrinsic base region in the electrically conductive layer.

Method of manufacturing a heterojunction BiCMOS integrated circuit

Insulated gate field effect transistors (10, 70) having process steps for setting the V.sub.T and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the V.sub.T and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the V.sub.T and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

Method for fabricating insulated gate field effect transistor having

A complementary insulated gate field effect transistor (10) having a partial channel. A gate electrode structure (29, 31) is formed on a dopant well (13, 14). An implant block mask (33, 38) is formed on a portion of the gate structure. An impurity material is implanted into the dopant well to form a dopant region (34, 39) having a first portion (36, 42) and a second portion (37, 41). The implant is of sufficient energy that a portion of the impurity material penetrates a portion gate electrode structure (29, 31) to form the second portion (37, 41) which serves as the partial channel. The partial channel provides the complementary insulated gate field effect transistor (10) with a low subthreshold swing, and improved saturation current and source/drain parasitic capacitance.

Insulated gate field effect transistor having a partial channel and

Growing community of inventors

Phoenix, AZ, United States of America

Vida Ilderem Burger