Digital Equipment Corporation

Victoria M Triolo

David W Hartwell

Elbert Bloom

Dennis F Hayes

A system permitting configuring of its total memory space includes a processor, an external operating device having a first address space and a bus coupling said central processing unit and the operating device. A starting address for the total memory space is defined and the operating device calculates its own starting address from the starting address of the total space.

Memory configuration system

A bus adapter connecting a high-speed pended bus to a slower speed non-pended bus includes a first module functioning as a node of the pended bus and a second module functioning as a node of the non-pended bus. An interconnect bus extends between the two modules. Control signals on the interconnect bus generated by the first module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the second module, which have a finite duration. Control signals on the interconnect bus generated by the first module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the second module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Method and apparatus for interconnecting busses in a multibus computer

A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a node on the pended bus. Control signals on the interconnect bus generated by the response module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the control module, which have a finite duration. Control signals on the interconnect bus generated by the response module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the control module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Bus adapter module for interconnecting busses in a multibus computer

A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

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Boylston, MA, United States of America

Victoria M Triolo