Micron Technology Incorporated

Smart Modular Technologies, Inc.

Victor Y Tsai

Neal Anthony Galbo

William Henry Radke

Peter Sean Feeley

Robert N Leibowitz

Theodore T Pekny

James Cooke

Danilo Caraccio

Daniele Balluchi

Robert Warren

Francesco Falanga

Bob Leibowitz

Terry R Lee

Chad A Cobbley

David K Ovard

Roy Edgar Greeff

Krishnam R Datla

Mehdi Asnaashari

Krishnam R Dalta

Neal A Galbo

Robert Fillion

The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Command queuing

Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Memory devices having special mode access

The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host.

State change in systems having devices coupled in a chained configuration

Memory devices and methods are described and shown that are capable of being configured in a chain. In one configuration, a single data input port and a single data output port are utilized at a host to communicate with the chain of memory devices. Methods for assigning identifiers to memory devices in the chain are described that include detection of a presence or absence of downstream memory devices. In selected examples, identifiers are assigned sequentially to memory devices in the chain until no additional downstream memory devices are detected.

Chained bus memory device

Approaches, techniques, and mechanisms are disclosed for a method of operation of a Flash-based block storage system including: transferring a first data to a logical block address; storing the first data in a physical block, of a storage array, associated with the logical block address; receiving a trim command for the logical block address; establishing a reserved physical block associated with the logical block address of the trim command; transferring second data for writing to the logical block address of the trim command; releasing the reserved physical block associated with the logical block address; and writing the second data to the logical block address.

Flash-based block storage system with trimmed space management and method of operation thereof

A memory device includes a serial interface controller that receives and operates using a serial message having a format that includes a command field of the serial message. The format also includes a register address field of the serial message immediately following the command field. The format further includes a data field of the serial message immediately following the register address field.

Memory devices having special mode access using a serial message

Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

Autorecovery after manufacturing/system integration

Growing community of inventors

Palo Alto, CA, United States of America

Victor Y Tsai