Taiwan Semiconductor Manufacturing Comp. Ltd.

Honeywell International Inc.

Novellus Systems Incorporated

Winbond Electronics Corporation

Victor Y Lu

Pu-Fang Chen

Chung-En Kao

Shi-Chieh Lin

Roger Leung

Feng Wang

Wen-Cheng Yang

Yeur-Luen Tu

Wai-Fan Yau

Brian Lu

Paul G Apen

Ya-Ling Lee

Lei Jin

Chih-Tsung Lee

Bo Li

Nerissa Sue Draeger

Su-Horng Lin

Ming-Chin Tsai

Yu-Young Wang

Arlene J Suedmeyer

Keng-Chu Lin

Cheng-Ta Wu

Shiang-Bau Wang

Yu-Hung Cheng

Ru-Liang Lee

Yu-Lung Yeh

Shing-Chyang Pan

Michael D Goodner

Nancy E Iwamoto

Makarem A Hussein

Joseph T Kennedy

Yen-Hsiu Chen

Songyuan Xie

Eric Chen Deng

Ananth Naman

Po-Jung Chiang

Brian J Daniels

Tsung-Hsun Yu

Mark A Fradkin

Surendra Babu Anantharaman

Wei Chin

Bart Jan Van Schravendijk

Michal Danek

Raashina Humayun

Yi-Hung Lin

Michael E Thomas

Chun-Yi Lee

Denis H Endisch

Maxim Kelman

Keith Kuang-Kuo Koai

Krishnan Shrinivasan

Sean C Chang

Tsung-Hsi Yang

Vishal Gauri

Lin-Jung Wu

Anil Shriram Bhanap

Wenya Fan

Lakshminarayana Nittala

De-Ling Zhou

Kie Jin Park

Kun-Mo Lin

Peter A Smith

Guangquan Lu

JingHong Chen

Deling Zhou

Wei-Zhe Chang

Shi-Jieh Lin

Jeong Seok Na

Tiffany Nguyen

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Structure for embedded gettering in a silicon on insulator wafer

A cleaning device for removing contamination on a substrate holder used with an electroplating cell includes an arm, a cleaning agent supplier, a nozzle and a receiver. The cleaning agent supplier is coupled to the arm and configured to supply a cleaning agent. The nozzle is coupled to the cleaning agent supplier and configured to spray the cleaning agent onto the substrate holder to remove the contamination. The receiver is coupled to the arm and configured to receive the cleaning agent after the cleaning agent is sprayed onto the substrate holder.

Cleaning device for cleaning electroplating substrate holder

Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Fabrication method of metal-free SOI wafer

A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising &#x3c;lmn&#x3e;, wherein l+m+n=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Semiconductor structure and method for manufacturing the same

Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.

Magnetic structure for metal plating control

Structure and method for embedded gettering in a silicon on insulator wafer

Cryogenic pump apparatuses include nanostructure material to achieve an ultra-high vacuum level. The nanostructure material can be mixed with either an adsorbent material or a fixed glue layer which is utilized to fix the adsorbent material. The nanostructure material's good thermal conductivity and adsorption properties help to lower working temperature and extend regeneration cycle of the cryogenic pumps.

Ultra high vacuum cryogenic pumping apparatus with nanostructure material

A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

Method for forming semiconductor device structure with etch stop layer

The present disclosure relates to some embodiments of a method for improving processing efficiency of a cluster tool. The method comprises transferring a first lot of wafers from a transfer load lock to a designated storage load lock and transferring a second lot of wafers from the transfer load lock to the designated storage load lock while the first lot of wafers is in the transfer load lock or the designated storage load lock. The designated storage load lock has the same structure as the transfer load lock and respectively has an inner load lock portal at an interface with the first transfer chamber and an outer load lock portal on a sidewall of a front end interface. The inner load lock portal of the designated storage load lock is retained opened during processing. The outer load lock portal of the designated storage load lock is retained closed during processing.

Cluster tool techniques with improved efficiency

A method of manufacturing a semiconductor structure includes the following operations. A wafer with an orientation mark at a first crystal orientation represented by a family of Miller indices comprising &#x3c;ijk&#x3e; is provided, wherein ijk=2. A first chip and a second chip are connected to a first surface of the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. The direction is not parallel to the first crystal orientation.

A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

Some embodiments relate to a cluster tool for semiconductor manufacturing. The cluster tool comprises a first transfer chamber having a first transfer robot. The cluster tool further comprises a designated storage chamber and a transfer load lock attached to the first transfer chamber. The cluster tool further comprises a second transfer chamber connected to the first transfer chamber through a pair of via connector chambers, the second transfer chamber having a second transfer robot. The cluster tool further comprises at least three epitaxial deposition chamber attached to the second transfer chamber. The cluster tool further comprises a control unit configured to control the second transfer robot to transfer wafers between the designated storage chamber and the transfer load lock.

Growing community of inventors

Foster City, CA, United States of America

Victor Y Lu