Emc Corporation

Victor W Tung

Stephen Lawrence Scaringella

Rudy M Bauer

Brian Arsenault

Gal Sne

Jeffrey Kinne

Paul C Wilson

William K Gross

A system and method for maintaining the integrity of data in a storage system. The method includes receiving a plurality of blocks of data having a predetermined multiple-block error detecting code; reading each block of the blocks of data; generating, for each block of data, an information-containing portion including an individual error detecting code for the block of data; and storing each block of data and each corresponding information-containing portion.

Data integrity management for data storage systems

A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Computer storage system incorporating on-board EEPROMS containing product data

The invention is directed to techniques that include an error detection code (e.g., a CRC code) and cleared bytes (e.g., zeroes) with data (e.g., CKD data). The use of cleared bytes with CKD data enables detection of corrupt CKD data by simply generating a CRC code based on an entire data block and comparing that generated CRC code with an initial CRC code appended to the CKD data within that data block. One arrangement of the invention is directed to a data storage system that includes a circuit having a memory pipeline that receives a stream of data elements, and provides a series of byte groups that includes the stream of data elements, an error detection code and a set of cleared bytes to a set of storage devices. Each of the series of byte groups provided by the memory pipeline has a same byte width. The inclusion of the error detection code and the set of cleared bytes enables consistent alignment of each byte group in the series.

Techniques for providing data within a data storage system

A system having a plurality of processors, each one of the processors being adapted to issue a control signal and a processor ID code. Each one of the processors has: a unique, pre-assigned processor ID code, and a common software program. The software program operates to: receive the control signal and the processor ID code from the issuing one of the processors along with an indication of the one of the processors which issued the particular control signal and processor ID code; and test whether the received processor ID code is the same as the processor issuing the command and if so, generate one of the broadcast mode or uni-cast modes; otherwise, generate the other one of the broadcast or uni-cast modes.

System having plural processors and a uni-cast/broadcast communication arrangement

A method and apparatus for controlling the flow of data through director elements of a disk drive controller are responsive to external clock signals to synchronize the internal clock timing of each director. The external clock signals are available over either a first master bus or a secondary master bus, each of the buses being connected to the director element. Each director element has circuitry which monitors the occurrence of clock pulses over the buses as well as circuitry for switching, upon the occurrence of a failure of clock pulses on the master bus, from the master bus to the secondary bus for the receipt and resynchronization of clock pulses.

Disk drive controller for controlling data flow therethrough by switching to secondary bus to receive clock pulses when a failure on master bus is detected

A hardware emulation controller permits a high performance processor to be used with system circuitry that is configured for operation with a different processor. The hardware emulation controller is capable of modifying signals from the high performance processor for compatibility with the system circuitry. The hardware emulation controller is also capable of modifying signals from the system circuitry for compatibility with the high performance processor.

Storage controller with hardware emulation controller for emulation between control processor and transfer circuitry compatible to different processor

System and method for maintaining synchronization in a computer storage system

A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The interface includes a system memory comprising a pair of system memory sections. Each one of the system memory sections has a plurality of addressable locations for storing data written into such one of the memory sections at the addressable locations. A pair of system busses is provided, each one of the pair of system busses being coupled to a corresponding one of the pair of system memory sections. A plurality of directors is coupled to the system memory through the system bus. The directors are configured to control data transfer between the host computer and the bank of disk drives as such data passes through the system memory. The directors are configured to place the system in a dual-write mode, and in such mode, store therein a burst of the data to be transferred between the host computer and the bank of disk drives, transfer such stored burst of data sequentially to the pair of system busses, and enable both of the system memory sections coupled to such pair of system busses to have written therein, at the same one of the addressable locations, the same burst of data transferred sequentially to the pair of system busses.

Data storage system

Computer storage system controller incorporating control store memory with primary and secondary data and parity areas

A method and a control device is provided for upgrading computer system hardware, for example, on a printed circuit board, with system revision information. The method includes receiving, a serial data stream having data bits associated with the system revision information through a serial input of the control device, determining the start of the data bits, and storing at least a portion of the data bits associated with the system revision information within a read-only register of the control device.

Method and apparatus for storing and retrieving system revision information

An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. Each control processor is responsible for 2 pipelines and respective Direct Multiple Access (DMA) and Direct Single Access (DSA) pipelines, for Global Memory access. Each processor has its own Memory Data Register (MDR) to support DMA/DSA activity. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides. Pipelines are extended to add greater depth by incorporating a prefetch mechanism that permits write data to be put out to transceivers awaiting bus access, while two full buffers of assembled memory data are stored in Dual Port Ram and memory data words are assembled in pipeline gate arrays for passing to DPR. Data prefetch mechanisms are included whereby data is made available to the bus going from Global Memory on read operations, prior to the bus being available for an actual data transfer. Two full buffers of read data are transferred from Global Memory and stored in DPR while data words are disassembled in the pipeline gate array, independent of host activity. Timing of system operations is implemented such that there is overlap of backplane requests to transfer data to/from memory, memory selection and data transfer functionality.

High performance integrated cached storage device

Redundant writing of data to cached storage system

An integrated cached disk array includes host to global memory (front end) and global memory to disk array (back end) interfaces implemented with dual control processors configured to share substantial resources. The dual processors each access independent control store RAM, but run the same processor independent control program using an implementation that makes the hardware appear identical from both the X and Y processor sides.

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Shrewsbury, MA, United States of America

Victor W Tung