International Business Machines Corporation

Chartered Semiconductor Manufacturing Ltd (corporation)

Victor W C Chan

Edward J Nowak

Brent A Anderson

Andrew Mark Greene

Gangadhara Raja Muthinti

Haining S Yang

Marc Adam Bergendahl

Xuefeng Liu

Min Yang

Roger Allen Booth, Jr

Yongan Xu

Michael P Belyansky

Jun Yuan

Yann A M Mignot

Jeffrey C Shearer

Huiling Shang

Narasimhulu Kanike

Yong Wee Lee

Varadarajan Vidya

Veeraraghavan S Basker

Junli Wang

Injo Ok

Su Chen Fan

Kisik Choi

Meikei Ieong

Jin Ping Han

MeiKei Leong

Samuel Sung Shik Choi

An integrated circuit includes a field effect transistor (FET) and a phase change memory (PCM) cell. The PCM cell includes a heater, wherein a bottom surface of the heater is at or below a top surface of the FET.

Heater for phase change material memory cell

A technique relates to a semiconductor device. One or more N-type field effect transistor (NFET) gates and one or more P-type field effect transistor (PFET) gates are formed. Source and drain (S/D) contacts are formed, at least one material of the S/D contacts being formed in the PFET gates. Insulating material is deposited as self-aligned caps above the NFET gates and the PFET gates, while the insulating material is also formed as insulator portions adjacent to the S/D contacts. Middle of the line (MOL) contacts are formed above the S/D contacts.

Single metallization scheme for gate, source, and drain contact integration

According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

Self-aligned gate cap including an etch-stop layer

Gate contact over active layout designs are provided. In one aspect, a method for forming a gate contact over active device includes: forming a device including metal gates over an active area of a wafer, and source/drains on opposite sides of the metal gates offset by gate spacers; recessing the metal gates/gate spacers; forming etch-selective spacers on top of the recessed gate spacers; forming gate caps on top of the recessed metal gates; forming source/drain contacts on the source/drains; forming source/drain caps on top of the source/drain contacts, wherein the etch-selective spacers provide etch selectivity to the gate caps and source/drain caps; and forming a metal gate contact that extends through one of the gate caps, wherein the etch-selective spacers prevent gate-to-source drain shorting by the metal gate contact. Alternate etch-selective configurations are also provided including a claw-shaped source/drain cap design. A gate contact over active device is also provided.

Gate contact over active enabled by alternative spacer scheme and claw-shaped cap

Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer. The gate contact is formed on top of the gate. A second layer is formed on the cap layer. The second layer and cap layer are recessed to remove a portion of the cap layer from a top part and upper sidewall parts of the gate contact. A third layer is formed on the second layer, cap layer, and gate contact. The third layer is etched through to form a gate trench over the gate contact to be around the upper sidewall parts of the gate contact. The gate trench is an opening that stops on the cap layer. Gate metal via is formed on top of the gate contact and around upper sidewall parts of the gate contact.

Avoiding gate metal via shorting to source or drain contacts

Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.

High threshold voltage NMOS transistors for low power IC technology

A structure fabrication method. A provided structure includes a gate dielectric region on the substrate and a gate electrode region on the gate dielectric region. Atoms are implanted in a top portion of the gate electrode region, which expands the top portion of the gate electrode in a direction parallel to a top surface of the gate dielectric region. After the atom implantation, a conformal dielectric layer is formed on top and side walls of the gate electrode region. A dielectric spacer layer, formed on the conformal dielectric layer, is etched such that only spacer portions of the dielectric spacer layer which are under the conformal dielectric layer remain, wherein for any point of the remaining spacer portions, a straight line through that point and parallel to a reference direction intersects the conformal dielectric layer. The reference direction is perpendicular to the top surface of the gate dielectric region.

Structure fabrication method

A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.

Semiconductor transistors with expanded top portions of gates

An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a &#x3c;001&#x3e; direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a &#x3c;110&#x3e; direction and the at least one NFET has a current flow in a &#x3c;100&#x3e; direction. The &#x3c;110&#x3e; direction is perpendicular to the &#x3c;100&#x3e; direction. A method of fabricating such as integrated semiconductor structure is also provided.

Substrate engineering for optimum CMOS device performance

A method for forming a semiconductor transistor with an expanded top portion of a gate The gate is expanded through implanting atoms in the top portion of transistor's gate electrode region. The transistor formed includes a semiconductor region having two source/drain regions and a gate dielectric region formed on the channel region between the source/drain regions. The gate electrode region is formed on the gate dielectric region. The gate electrode region is formed such that it is electrically insulated from the channel region by the gate dielectric region. The top of the gate electrode region formed is wider than the bottom of the gate electrode region.

A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

Growing community of inventors

Guilderland, NY, United States of America

Victor W C Chan