Nxp B.v.

Victor Van Acht

Nicolaas Lambert

Pierre Hermanus Woerlee

Hans Boeve

Teunis Jan Ikkink

Karen Attenborough

Albert W Marsman

Niek Lambert

Nick Lambert

Teunis Jian Ikkink

A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.

Programmable phase-change memory and method therefor

A non-volatile memory is disclosed. A contiguous layer of phase change material () is provided. Proximate the contiguous layer of phase change material () is provided a first pair of contacts () for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material () for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts () disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material () for inducing heating thereof within a second region thereof, the second region different from the first region. This pairs of contacts may be disposed on the same side or on opposing sides of the phase change material layer.

A circuit comprises an array of memory cells (). A plurality of sensing circuits (), are coupled to the output () of respective memory cells (), for comparing the output signal of the respective one of the memory cells () with a reference signal to form a data signal from the output signal from the respective one of the memory cells (). A reference generator circuit () forms the reference signal from a sum wherein each respective one of the memory cells () of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.

Circuit with a memory array and a reference level generator circuit

Systems comprising generating devices comprising sensors for generating sensor signals representing orientations of the generating devices are provided with comparing devices comprising comparators for comparing the sensor signals with reference signals for interpreting the orientations, to increase the number of possible applications. The generating devices and the comparing devices may form parts of one apparatus or of different apparatuses and then communicate wiredly or wirelessly via radio or infrared. Reference sensors for generating the reference signals and/or reference memories for storing the reference signals may be located in the comparing devices and/or in sources and then communicate wiredly or wirelessly via radio or infrared. Further comparators in the comparing devices may introduce adjustable sensitivities.

System comprising a generating device and a comparing device

A memory matrix () comprises rows and columns of cells, each cell comprising a resistance hysteresis element () and a threshold element () coupled in series between a row terminal and a column terminal of the cell (). The resistance hysteresis element () has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell () is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform erase actions, all cells () of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells () in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells () that are selected dependent on write data.

Driving a memory matrix of resistance hysteresis elements

A control circuit () for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second. During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state () during execution of an all column update command. The control circuit () is retained in the first and second idle state (II,), without switching to the second and first idle state (, II) between execution of successive column selective update commands and all column update commands respectively.

Growing community of inventors

Waalre, Netherlands

Victor Van Acht