Atmel Corporation

Victor V Nguyen

Saroj Pathak

James E Payne

Nicola Telecco

Harry H Kuo

A circuit and method for producing an output voltage that replicates an input voltage. A circuit comprises an amplifier stage configured to amplify a difference between an input voltage and a feedback voltage. An output stage is configured to produce an output voltage equal to the input voltage. The output stage configured to be driven by the difference between the input voltage and the feedback voltage. The output stage further comprises a main supply current path configured to provide a first current from a main supply source, the first current providing at least a portion of the output voltage, and a current management circuit configured to provide a second current from an auxiliary supply source, the second current providing any remaining portion of the output voltage not provided by the first current.

Unity gain voltage buffer with dual supply voltage for managing current consumption in low voltage applications

The present invention is related to semiconductor memories, and in particular, to a nonvolatile or flash memory and method that reduces the effect of or is tolerant of over-erased memory cells. When a memory cell is read, a read voltage is applied to at least one target memory cell, and a negative bias voltage that is lower than a threshold voltage of an over-erased memory cell is also applied to at least one other selected memory cell that is in the same row as the target memory cell. Applying a negative bias voltage to adjacent or proximate memory cells shuts off nearby cells to isolate current that may come from over-erased memory cells during a read, program, or erase operation.

Memory architecture with enhanced over-erase tolerant control gate scheme

A programmable logic device (PLD) architecture includes a plurality of PLD single-bit logic cells. Each single bit logic cell is comprised of all CMOS logic devices including a programmable cell unit, a settable latch, a signal path with inverter, and an output logic gate. The single path is coupled to the cell unit, the settable latch, and the output logic gate to create a positive feedback loop to improve speed and noise immunity. Each single bit logic gate is a basic building block for a modular low power consumption, high speed, zero DC current, high noise immunity programmable logic device (PLD) which includes an array of word lines and bit lines arranged in rows and columns for addressing, an array of OR gates, and a plurality of output logic circuits.

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San Jose, CA, United States of America

Victor V Nguyen