National Semiconductor Corporation

Victor Torres

Rodney L Hill

Terry Lee Lines

William Max Coppock

Richard W Foote, Jr

Tom Bold

Michael Burger

Richard Wendell Foote, Jr

Thomas Bold

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. First and second portions of a first dielectric material are formed over the resistor protect layer over the first and second ends of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the first dielectric material as a hard mask. Then a second dielectric layer is deposited. A first via mask and etch process is used to etch vias down to the underlying portions of the resistor protect layer over the ends of the thin film resistor. A second via mask and etch process is used to etch substrate vias to an underlying conductor layer.

System and method for providing a dual via architecture for thin film resistors

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

System and method for providing a buried thin film resistor having end caps defined by a dielectric mask

A method is disclosed for applying a plasma etch process to facet a masking layer in a semiconductor device by creating sloped surfaces in the masking layer. The masking layer is plasma etched with a plasma that has a high sputter etch component. The plasma etch process removes material from vertical edges of the masking layer to form a sloped surface at each vertical edge of the masking layer. A layer of conductive material is then applied to the masking layer. When the layer of conductive material is subsequently removed by an overetch process the sloped profile of the masking layer facilitates the removal of stringers of conductive material without using an excessively lengthy overetch.

System and method for faceting a masking layer in a plasma etch to slope a feature edge

A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.

System and method for faceting via top corners to improve metal fill

A system and method is disclosed for selectively increasing a wet etch rate of a large raised area portion of a semiconductor wafer with respect to a wet etch rate of a small raised area portion of the semiconductor wafer. A resist mask on the semiconductor wafer is etched to create a large via over the large raised area portion and a small via over the small raised area portion. An ion implantation beam is applied with an impact direction that enables ions to pass through the large via but does not enable ions to pass through the small via. The ions that pass through the large via increase the wet etch rate of the underlying portion of the semiconductor wafer. In one embodiment the impact direction has a tilt angle of forty five degrees and a rotation angle of forty five degrees.

System and method for selectively modifying a wet etch rate in a large area

A system and method is disclosed for providing a dry-wet-dry etch procedure to create a sidewall profile of a via in a semiconductor device. A first vertical anisotropic dry etch process is applied to etch through a first portion of a dielectric layer. An isotropic wet etch process is then applied to etch a sloping surface in the sidewalls of the via cavity. A second vertical anisotropic dry etch process is then applied to extend the sloping sidewalls of the via cavity down to a substrate of the semiconductor device. The smooth sloping surfaces of the sidewalls are formed without a prior art concave surface of the type that interferes with a via fill process.

Growing community of inventors

Irving, TX, United States of America

Victor Torres