International Business Machines Corporation

Cisco Technology, Inc.

Cisco Systems Inc.

Victor Spagnol

Claude R Galand

Gerald Lebizay

Andre Pauporte

Edward Stanely Suffern

Aline Fichou

Jean-Marie L Munier

Daniel Mauduit

Philippe Pierre Louis

Simon Huon

Jean M Munier

Eric Saint-Georges

Xavier Jacquart

Frederic J Bauchot

Ilias Iliadis

Jean L Calvignac

Didier F Giroir

Jean-Marc Berthaud

Hong Linh Truong

Pierre-Andre Foriel

Michel F Choquet

Clement Y Poiraud

Jacques Belloc

Daniel Pilost

Jean Cholat-Namy

Firmin Bigo

Marcus Enger

Francois De Saint Michel

Bruno Sappa

Pierre Gerardin

Eric S Georges

Patrick Massi

Jean-yves Leboudec

Georges Gallet

Jean-Marie Munier

Daniel G Mauduit

Method for optimizing a digital transmission network operation through transient error monitoring and control and system for implementing said method

A packet scheduling system for use in a switching node of a high speed packet switching network. Incoming packets are enqueued in connection queues. Each connection is classified as red (exceeding traffic profile) or green (within traffic profile). QOS priority is also identified for each connection. Packets are dequeued for transmission as a function of priority class and connection class. Higher priority class connections have priority over lower priority class connections. Within a given priority class of connections, green connections have priority over red connections. Round robin scheduling is used for packets from connections in the same priority and connection class. In addition, a dynamic priority coupling mechanism is provided to prevent red higher priority traffic from blocking green lower priority traffic.

Multiple-criteria queueing and transmission scheduling system for multimedia networks

A method and system for optimizing data link occupation in a multipriority data traffic environment by using data multiplexing techniques over fixed or variable length data packets being asynchronously transmitted. The packets are split into segments including both a segment number and a packet number. The segments are dispatched, on a priority basis, over available links or virtual channels based on a global link availability control word indications, which control word is dynamically adjusted according to specific predefined conditions.

Method and system for optimizing data transmission line bandwidth

Traffic congestion control is provided for a network node multiport switch capable of switching data packets of different priorities from input lines, via receive adapters, to output lines via transmit adapters. A spacing function is performed to limit the rate of data transfers through the switch in the absence of high priority data at the input lines and in the absence of a backpressure signal indicating the switch is congested at its output. If high priority data is detected or a backpressure signal has been generated, the data transfer rate is increased to deal with possible congestion.

Method and system for performing traffic congestion control in a data

A data transmission network congestion control mechanism requires knowledge of the sequence of occurrence of two dates d1 and d2, respectively defined by times t1 and t2 provided by a wraparound timer as respective numbers A and B coded in a 2's-complement form. Relative date discrimination is implemented by dividing the wraparound timer period into four consecutive intervals, each defined by the two most significant bits of the timer count. The value of the most significant bits and the sign of A-B, are used to derive a one-bit 'X' indicator, the binary value of which indicates which of the two dates d1 and d2 was first to occur.

Method and system for implementing relative time discriminations in a

A method and an apparatus to calculate in an intermediate node of a communication network, the new Frame Check Sequence (FCS) appended to a data bits message which has been modified in said intermediate network node. The invention is useful for high speed networks where the transit delay needs to be optimized in the network along with the computing resources in the intermediate network nodes in terms of computer cycles and memory size. The invention consists in calculating the difference between the FCS using the difference between the modified fields in the message and the distance in bits between the end of the modified field and the end of the message; the calculation consists in differentiating `short messages` in the data flow and to provide an optimized processing for the short messages, the processing for larger messages being based on this first optimized processing. The calculation of the modified FCS comprises operations on polynomials whose coefficients belong to the Galois's Field and whose degree is limited to the one of the polynomial generator of the corresponding CRC code. The calculations include also look up operations in tables limited in size. The choice between the possible implementations (full software, full hardware and mixed hardware and software with the usage of a Remult operator for the last two) will depend on the kind of the network (Frame Relay or other network) and the capacity of the intermediate network node.

Method and an apparatus to modify CRC in intermediate high speed network

The present invention relates to an efficient point-to-point and multi-points routing system and method for programmable data communication adapters in packet switching nodes of high speed networks. The general principles of this efficiency are the following:

Efficient point-to-point and multi-point routing mechanism for

A multipurpose data communication network node for interconnecting both ATM and Variable Length (VL) input/output trunks with all combinations of node input versus output trunk connections. The network node includes ATM/VL Receive Adapters and ATM/VL Transmit Adapters, interconnected via a Switching device (44) operating on ATM like packets (i.e. ATM cells) only. The receive adapter includes means (41, 43) for deriving switchable cells from VL traffic possibly including ATM packets and provided over an input VL trunk and means (45, 46) for deriving switchable cells from ATM packets provided on input ATM trunk. The transmit adapter, includes means (47, 48) for reconstructing VL traffic to be fed onto an output VL trunk, and means (49, 50) for reconstructing ATM traffic to be fed onto an output ATM trunk; both means (47, 48) and (49, 50) being fed with switchable cells irrespective of the traffic origin, being it from VL or ATM trunks.

Multipurpose packet switching node for a data communication network

In a packet switched communications system an incoming real-time packet is imbedded after the next block of data of the non-real-time packet being transmitted. This object is accomplished by transmitting each packet along with at least a 1-byte trailer which is used to indicate the packet type, whether the current block of non real time data is preempted or whether the current block of non real time data is resumed.

Method and apparatus for transmission of high priority traffic on low

A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises

Programmable high performance data communication adapter for high speed

Fast scheduling mechanism of tasks to be performed in a communication system, like a modem, and the scheduler for implementing the mechanism. The communication system receives, synchronously to a rate determined by a high priority program, data to be processed by the tasks of a lower priority main program. Instead of scheduling the tasks immediately upon requests generated by an interrupt program, said tasks are scheduled with a controled delay relatively to their corresponding requests. Thus, free processing windows are created for execution of asynchronous tasks or synchronous transient overloads. Overall, more synchronous and asynchronous tasks can be performed without increasing processing power.

Synchronous communications scheduler allowing transient computing

According to the invention, a data transmission system is provided with apparatus which enables the problem determination requests from any ports of the multiplex modems (18) to be processed. When a link event is detected on a port or when a solicited command is received from a host network management facility computer (10), the network control program (NCP) in the communication controller (16) checks with the associated link configuration data as to whether the involved port is port A. If is not port A, NCP looks for port A which has the same NCP correlation number as the involved port. Then, the LPDA message can be sent through port A and can reach the remote corresponding port A if necessary.

Data transmission system with a link problem determination aid (LPDA)

A DTE can control the modems attached thereto by transmitting command messages over the data path and analyzing report messages supplied by the modems in return. Each command message is identified by a specific header. A command message intended for a remote modem (34) is intercepted by the local modem (30) and reformatted so as to obtain a supervisory message that is then transmitted at the rate of one bit per baud. A command message intended for a remote multichannel modem (48) is transmitted either by a supervisory message or in the data mode of operation.

Method and system for controlling a network of modems

Memory 60 contains a decision table which is a replica of the particular N-bit pattern to be detected. When a bit is received over line 12, a table lookup operation is performed to determine whether the entry at the address indicated by address counter 34 contains a bit that matches the received bit. If so, the content of the address counter is incremented by one and the device waits for another bit to be received over line 12. If the bit in the entry does not match the received bit, then, if the address indicated by the counter is zero, the count of the counter is maintained at zero and the device waits for another bit to be received; or, if the address is different from zero, the counter is reset to zero and the bit present on line 12 is again presented to the table in order, this time, to be compared with the bit in the entry at address zero. The pattern is detected when the address contained in the counter is equal to N and when the last bit in the pattern matches the bit with which it is compared.

Method and device for detecting a particular bit pattern in a serial

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Cagnes sur Mer, France

Victor Spagnol