Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Victor Seng Keong Lim

Wang Ling Goh

Alex See

Liang Choo Hsia

Fang Hong Gn

Young-Way Teh

Lap Chan

Ting Cheong Ang

Randall Cher Liang Cha

Yeow Kheng Lim

Feng Chen

Rachel Yie Fang Wai

Jeffrey C Lam

Yong Kong Siew

Chen Feng

James Yongmeng Lee

Ting-Cheong Ang

Barbara Fong Chin Lim

Keng Heng Lai

Tanya Yang

A method of forming a device is presented. The method includes providing a substrate containing at least a partially formed device thereon. The device comprises at least one defect site. A pixilated image of the defect site is acquired, and each pixel comprises a grey level value (GLV). Surrounding noises of the defect site is eliminated. A point of the image is identified as the center of the defect. A plurality of iterations to exclude outer edge pixels surrounding the center of the defect image is performed. The defect is categorized as a killer or non-killer defect.

Defect monitoring in semiconductor device fabrication

A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

Defect detection recipe definition

A method of forming a device is disclosed. The method includes providing a substrate on which the device is formed. It also includes forming a test cell on the substrate. The test cell includes a defect programmed into the cell to facilitate defect detection.

Test chiplets for devices

A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.

E-beam inspection structure for leakage analysis

A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

Extended poly buffer STI scheme

A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.

Copper metal structure for the reduction of intra-metal capacitance

A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application

A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Method for fabricating an air gap shallow trench isolation (STI) structure

A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

Method to achieve STI planarization

A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.

Growing community of inventors

Singapore, Singapore

Victor Seng Keong Lim