Motorola Corporation

Victor S Wang

Philip J Tobin

David L O'Meara

Rama I Hegde

Hsing-Huang Tseng

Bich-Yen Nguyen

William James Taylor, Jr

Yeong-Jyh Tom Lii

Percy V Gilbert

In accordance with one embodiment of the present invention, a method is disclosed for forming a semiconductor device having an isolation region ( ). A dielectric layer ( ) is deposited and etched to form isolation regions ( ) having top portions that are narrower than their bottom portions, thereby a tapered isolation region is formed. Active regions ( ) are formed using an epitaxial process in the regions between the isolation regions. The resulting active regions ( ) have a greater amount of surface area near a top portion, than near a bottom portion. Transistors ( ) having opposite polarities are formed within the active areas.

Method for forming a semiconductor device with an opening in a dielectric layer

A method for forming an oxynitride gate dielectric layer (,) begins by providing a semiconductor substrate (,). This semiconductor substrate is cleaned via process steps (,). Optional nitridation and oxidation are performed via steps (,and,) to form a thin interface layer (,). Bulk oxynitride gate deposition occurs via a step (,) to form a bulk gate dielectric material (,) having custom tailored oxygen and nitrogen profile and concentration. A step (,) is then utilized to in situ cap this bulk dielectric layer (,) with a polysilicon or amorphous silicon layer (,). The layer (,) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (,) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.

Process for forming a semiconductor device

A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.

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Austin, TX, United States of America

Victor S Wang