International Business Machines Corporation

Victor Paul Seidel

Joseph Andrew Iadanza

Terrance John Zittritsch

Frank Ray Keyser, Iii

Scott Whitney Gould

Kim P Clinton

Ralph David Kilmoyer

Michael Joseph Laramie

A field programmable memory array having a plurality of sub-arrays is provided. Programmable address decoders, programmable hierarchical bit line arrangements, programmable I/O arrangements, among other features, are provided to enable programming of portions of the array into selected modes. The modes may include wide memory, deep memory, FIFO, LIFO, among others. An embodiment of the invention is disclosed wherein the field programmable memory array is integrated with the programmable resources of a field programmable gate array.

Field programmable memory array

Memory cells for field programmable memory array

Selective connectivity between memory sub-arrays and a hierarchical bit

According to the present invention an improved device and method for testing the integrity of electrical connectors on a substrate and/or for providing for burn-in of a semi-conductor on a substrate is provided. The test unit includes a mounting fixture having a plurality of pins carried thereon preferably spring loaded. At least some of the pins are provided with a plurality of circumferentially spaced conducting members which are electrically insulated from each other. These pins are configured and mounted on the fixture to move into and out of engagement with a portion at least two and preferably four adjacent connectors on the substrate thereby allowing a single pin to contact up to four or more contacts on the substrate. In addition to the single pin contacting four or more connectors, the pins are configured such that they fit between the connectors rather than resting on top of them with the electrically conducting members contacting the sides of the solder balls thereby providing a extended contact surface as opposed to contacting the tops of the connectors on the substrate. Each of the separate conducting members on the pins is connected to a test circuit and/or a burn-in circuit which provides the appropriate test signals and/or power to the various connectors on the substrate.

Apparatus for testing circuits and/or burning-in chips

Method of testing circuits and/or burning-in chips

Growing community of inventors

Burlington, VT, United States of America

Victor Paul Seidel