Synopsys, Inc.

Applied Materials, Inc.

Kawa, Jamil

Moroz, Victor

Sproch, James D.

Lefferts, Robert B.

Victor Moroz

Jamil Kawa

Xi-Wei Lin

Dipankar Pramanik

Stephen Lee Smith

Yong-Seog Oh

Michael C Shaughnessy-Culver

Jie Liu

Terry Sylvan Kam-Chiu Ma

Deepak Dattatraya Sherlekar

Pratheep Balasingam

James David Sproch

Lars Bomholt

Tsu-Jae King

Xiaopeng Xu

Stephen Robert Whiteley

Qiang Lu

Munkang Choi

Aditya Pradeep Karmarkar

Lori D Washington

Robert Beverly Lefferts

Faran Nouri

Karim El Sayed

Thu V Nguyen

Michael Lawrence Rieger

Tsu-Jae King Liu

Ignacio Martin-Bragado

Kishore Singhal

Salvatore Maria Amoroso

Zudian Qin

Joanne Huang

Andrew Edward Horch

Hiu Yung Wong

Mark Edward Rubin

Philippe Roussel

Plamen A Asenov

Xi Wei Lin

Ibrahim Avci

Ivan Ciofi

Shuqing Li

Andrey Kucherov

Robert B Lefferts

A method of forming a multitude of GAAFETs on a silicon substrate includes forming alternating layers of Si nanosheets and SiGe alloys above the silicon substrate, depositing a layer of oxide buffer above the top layer of SiGe alloy, depositing a mask layer above the oxide buffer layer, patterning the mask and the oxide, and performing a RIE of the silicon nanosheet and SiGe alloy layers so as to form tapered pillars of silicon nanosheet and SiGe alloy layers. In each tapered pillar, a width of the first layer of silicon nanosheet that is closer to the substrate is greater than a width of the etched second layer of silicon nanosheet that is formed above the first layer of silicon nanosheet. The first, and second tapered silicon nanosheet layers in each pillar form channels of first and second GAAFETs.

Stacked nanosheet device for process and performance optimization

A structure may include a set of metal layers disposed on a substrate layer, where a dielectric material is disposed between adjacent metal layers in the set of metal layers. The structure may include a first superconducting structure and a second superconducting structure created in a metal layer selected from the set of metal layers. The first superconducting structure may have a first length along a first direction which is parallel to a primary routing direction of the metal layer, a second length along a second direction which is parallel to the substrate layer and perpendicular to the first direction, and a third length along a third direction which is directed away from the substrate layer and perpendicular to the first direction and the second direction. The third length may be greater than the second length.

Interconnects, inductors, transformers, and power architectures for circuits

A configuration to isolate ion implantation of silicon channels for placement of integrated circuit devices within an integrated circuit layout. The configuration layers a photolithographic mask having one or more openings on a silicon substrate. The configuration directs a focused ion beam towards the silicon substrate to implant ions in the silicon substrate at the one or more openings in the photolithographic mask. The configuration anneals the silicon substrate with the layered photolithographic mask to activate a reaction between silicon of the silicon substrate and the implanted ion to achieve an ionized formation in the silicon substrate.

Isolating ion implantation of silicon channels for integrated circuit layout

A method includes instantiating a first plurality of rows in a first region of a fabric. The first region has a height corresponding to a sum of heights of the first plurality of rows. The method also includes instantiating a second plurality of rows in a second region of the fabric. The second region is horizontally adjacent to the first region in the fabric. The second region has a height corresponding to a sum of heights of the second plurality of rows. The method further includes determining whether a row of the first plurality of rows is misaligned with a row of the second plurality of rows and adding a transition region between the row of the first plurality of rows and the row of the second plurality of rows in response.

Adaptive row patterns for custom-tiled placement fabrics for mixed height cell libraries

A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.

Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET)

Josephson junction (JJ) structures are disclosed. In some embodiments, a JJ structure may include alternating planar superconducting structures and planar non-superconducting structures arranged along a direction away from a wafer surface.

Josephson junction structures

Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Power routing for 2.5D or 3D integrated circuits including a buried power rail and interposer with power delivery network

Integrated circuit devices which include a thermoelectric generator which recycles heat generated by operation of an integrated circuit, into electrical energy that is then used to help support the power requirements of that integrated circuit. Roughly described, the device includes an integrated circuit die having an integrated circuit thereon, the integrated circuit having power supply terminals for connection to a primary power source, and a thermoelectric generator structure disposed in sufficient thermal communication with the integrated circuit die so as to derive, from heat generated by the die, a voltage difference across first and second terminals of the thermoelectric generator structure. A powering structure is arranged to help power the integrated circuit, from the voltage difference across the first and second terminals of the thermoelectric generator. The thermoelectric generator can include IC packaging material that is made from thermoelectric semiconductor materials.

Power harvesting for integrated circuits

A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth in a lower level of the CFET, adding a contact material to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot of the unfinished CFET structure, adding a conductive material within a vertical channel, the conductive material being in contact with the added contact material and the BPR to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.

Forming a wrap-around contact to connect a source or drain epitaxial growth of a complimentary field effect transistor (CFET) to a buried power rail (BPR) of the CFET

A memory cell comprises a pair of cross-coupled inverters as a storage element, a first inverter in the pair of cross-coupled inverters having a first output at a first node, a second inverter in the pair of cross-coupled inverters having a second output at a second node. A first complementary transmission gate includes a first nMOS pass gate and a first pMOS pass gate, connected between the first node and a first bit line. A second complementary transmission gate includes a second nMOS pass gate and a second pMOS pass gate, connected between the second node and a second bit line. A first word line is connected to gate conductors of the first and second nMOS pass gates in the first and second complementary transmission gates. A second word line is connected to gate conductors of the first and second pMOS pass gates in the first and second transmission gates.

CFET SRAM cell utilizing 8 transistors

The independent claims of the present disclosure signify a concise description of embodiments. An electronic structure based on complementary-field effect transistor (CFET) architecture is disclosed. The electronic structure comprises an n-channel metal-oxide-semiconductior (NMOS) gate-all-around (GAA) channel in a first layer, and p-channel metal-oxide-semiconductor (PMOS) GAA channel in a second layer. The PMOS GAA channel is wider compared to the NMOS GAA channel. The first layer is above the second layer and separated by a dielectric layer.

CFET architecture for balancing logic library and SRAM bitcell

At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

Fin patterning to reduce fin collapse and transistor leakage

A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more SiOprotective layers, etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the SiOprotective layer, and performing epitaxial growth on the upper level.

Epitaxial growth of source and drain materials in a complementary field effect transistor (CFET)

A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Fabrication technique for forming ultra-high density integrated circuit components

A method of forming a multitude of vertical NAND memory cells, includes, in part, forming a multitude of insulating materials on a silicon substrate, forming a trench in the insulating materials to expose a surface of the silicon substrate, depositing a layer of polysilicon along the sidewalls of the trench, filling the trench with oxide, forming a metal layer above the trench, and forming a mono-crystalline channel for the NAND memory cells by applying a voltage between the silicon substrate and the metal layer to cause the polysilicon sidewalls to melt. The melted polysilicon sidewalls is enable to recrystallize into the mono-crystalline channel.

Electro-thermal method to manufacture monocrystalline vertically oriented silicon channels for three-dimensional (3D) NAND memories

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Saratoga, CA, United States of America

Victor Moroz