Honeywell Information Systems Inc.

Victor Michael Griswold

Jaime Calle

Jerome J Twibell

An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted. The processor responds to a timer interrupt request by a special command which can only selectively clear the rollover counter to ZEROS when the interval counter is not in the process of completing another interval.

Interval timer for use in an input/output system

An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits. The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation. The processing unit in control stores information in the memory unit to specify the interrupt priority level of the connect operation, sets an interrupt request at that same priority level, and causes an interrupt at a very high priority level for the other processing unit via the intercommunication network. The high priority level interrupt causes the other processing unit to execute instructions which load the priority level information from the memory unit and set an interrupt request at the specified level. With both processing units having outstanding interrupt request at the specified priority level, the processing unit which completes all of the processes at priority levels higher or equal to that of the queue entry responds to the interrupt first. By having the least busy processing unit respond to the interrupt utilizing the queue entry to initiate the desired input/output operation process, a balance in the utilization of the input/output processing units is insured.

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Phoenix, AZ, United States of America

Victor Michael Griswold