Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Bull Nh Information Systems, Inc.

Victor M Morganti

Patrick E Prange

James B Geyer

George J Barlow

James W Keeley

Virendra S Negi

Arthur Peters

Richard C Zelley

Elmer W Carroll

Wallace A Martland

Michael J Graesser

In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group. The interprocessor communication has only a minor impact on the performance of the source processor and the target processor because of the command implementation by apparatus.

Apparatus and method for interprocessor communication

A data processing unit includes a number of tightly coupled central subsystems, a number of peripheral subsystems, a main memory and a system management facility all coupled in common to a system bus. The system management unit has top priority on the system bus and includes centralized resources which provide apparatus for indicating the status of power and temperature, booting the subsystems, testing the subsystems, timing central subsystem functions, and allowing local and remote maintenance access to the subsystems. The system management facility receives commands from the central subystem to read from and write into the timers as well as to read the status of the overall system. The system management facility generates special commands to the central subsystem to indicate when the timers have decremented to ZERO as well as special commands to aid in hardware and software debugging.

Multiprocessor system with centralized initialization, testing and

In a data processing system, a measurement of the cumulative time used in the performance of an intermittent activity can be required. To determine this cumulative time, a memory location is designated during initialization that is to contain the value of the system clock determined at each initiation of the intermittent activity. A second memory location is provided during initialization that is to contain the accumulated total of the measurements taken to perform the intermittent activity. At each termination of the intermittent activity, the contents of the first and second locations are retrieved from the main memory. The value stored in the first main memory location is then subtracted from the system clock value at the termination of the current intermittent activity and the resulting value is added to the contents of the second location. The resulting value of the addition operation is then stored in the second main memory location. This procedure is implemented with a single instruction and the instruction uses processor working registers for intermediate storage to expedite execution of the instruction.

Single instruction updating of processing time field using software

In combination with a multiprocessing and multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new architecture for the execution of the call instruction, the return instruction, and the trap procedure is implemented partly in firmware and partly in hardware. The architecture includes a new stack mechanism for storing hardware managed control information in a control frame and software controlled data in a data frame.

Call instruction, return instruction and trap procedure for ring

In a multiprocessor, multiprogrammed data processing system employing virtual addressing, apparatus and method are provided for selecting a page frame in a main memory unit to be replaced by a new page frame of logic signal groups required by a processor. Rather than utilize an algorithm implemented in a series of logical decisions determined by a software procedure, the present invention provides for a single instruction that uses the status signals included with a page descriptor to address an entry in a table of resulting status signals. The relationship between the status signals and the table entries implements the algorithm. The table with entries of resulting status signals is associated with the instruction and is stored in the processor when the instruction is prepared for execution by the processor. The resulting status signals are stored with the page descriptor, replacing the original status signals. The resulting status signals are analyzed by a software procedure, the software procedure implementing the page replacement activity and executing other activity indicated by the resulting status signals.

Apparatus and method for implementation of a page frame replacement

In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

P and V instructions for semaphore architecture in a

In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism stores hardware managed control information in a control frame and software controlled data in a data frame.

Call instruction for ring crossing architecture

An alphanumeric search apparatus wherein a plurality of search indicia stored in a first operand and a plurality of elements stored in a second operand are operated upon by a data processing system to determine by means of search or verify operations whether any of the elements included in the second operand correspond to any one of the indicia included in the first operand. The second operand may be arranged in a sequential string of elements or in an array or table of elements and a search is conducted by comparing each element sequentially with all the search indicia and by so processing the elements until a match is found. A verify procedure is conducted by comparing each element with the search indicia to verify that there is a counterpart for each search element in the list of search indicia. For a search procedure, an output is generated indicating the storage locations within their respective operands of the search indicia and the element which produced the match. For a verify procedure an output is generated indicating the first storage location of a search element that is not included in the list of search indicia.

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Lincoln, MA, United States of America

Victor M Morganti