Nxp B.v.

St-Ericsson Sa

Victor M G Van Acht

Nicolaas Lambert

Sebastian Egner

Pierre Hermanus Woerlee

Paul Van Der Sluis

Martinus Wilhelmus Blum

Hans M B Boeve

Ludovicus M G M Tolhuizen

Andrei Mijiritskii

Albert W Marsman

Johannis F R Blacquiere

Teunis J Ikkink

A main memory () comprises a plurality of physical blocks of memory locations. The main memory () supports erasing of at least a physical block at a time. Pointer information is stored in a subset () of the blocks for use to identify respective ones of the physical blocks that are assigned to respective functions. Successive versions of the pointing information are stored at mutually different memory locations initially in a first block () in the subset (). A subsequent version of the pointing information that is more recent than the successive versions is stored in a second block () of the subset () at least after the first block () has been filled. The first block () is erased after storing the subsequent version. On start up of the main memory the pointing information is recovered by testing which of the blocks of the subset () contains a most recent version of the pointing information.

Non-volatile memory with block erasable locations

A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given the information. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.

Data storage and replay apparatus

Data is read from a memory matrix () with a plurality of bit lines (). A differential sense amplifier () receives a signal derived from a first one of the bit lines () on a first input. The differential sense amplifier () receives a reference signal from a reference output of a reference circuit () to a second input. A second one of the bit lines (), which is adjacent to the first one of the bit lines (), is coupled to the reference circuit (), so that a bit line signal value on the second one of the bit lines () affects a reference signal value on the reference output, at least partly reproducing an effect of crosstalk of the bit line signal value () on the second one of the bit lines () on a bit line signal value on the first one of the bit lines ().

Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation

A One Time Programmable (OTP) memory cell () comprising a first, metallic layer () coated with a second, conductive stable transition compound () with an insulating layer () there-between. The first and second layers () are selected according to the difference in Gibbs Free Energy between them, which dictates the chemical energy that will be generated as a result of an exothermic chemical reaction between the two materials. The materials of the first and second layers () are highly thermally stable in themselves but, when a voltage is applied to the cell (), a localized breakdown of the insulative layer () results which creates a hotspot () that sets off an exothermic chemical reaction between the first and second layers (). The exothermic reaction generates sufficient heat () to create a short circuit across the cell and therefore reduce the resistance thereof.

Anti-fuse memory device

An apparatus comprises a memory with a matrix () with rows and columns of memory cells. A read access circuit () executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix () and to output data from the retrieval unit. A processing circuit () coupled to the read access circuit () is configured to execute an extra read operation involving issuing the read command, receiving the extra data (), performing error detection on only the extra data (), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data () using data from the retrieval unit including the payload data (), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (). The processing circuit () performs further processing using the data from the extra data () or the corrected extra data, dependent on whether the error detection indicates an error in the extra data ().

Electronic circuit with a memory matrix that stores pages including extra data

A data processing circuit comprises an encoder circuit for encoding a data word, wherein each digit may have any one of three or more digit values. The data word is encoded so that digit counts in the data word satisfy predetermined criteria (the digit counts are counts of the numbers of the digits in the encoded data word that assume respective digit values). The encoder defines at least two digit maps, each digit map defining assignments of each of the available digit values to a respective different output digit value. The encoder selects at least two groups of digits within the input data word. Each group is associated with a respective one of the digit maps, the groups being selected so that when each digit map has been applied selectively to the digits from its associated group, digit counts of the number of times respective digit values occur in the data word will satisfy predetermined criteria. A data signal is generated that represents the input data word by information that identifies the selected groups and an output data word obtained by mapping the digits of each group in the input data word according to the digit map for that group.

Encoding of data words using three or more level levels

The present invention relates to a non-volatile memory device, comprising a memory array () with a plurality of memory cells () arranged in rows and columns, bit line conductors () coupled to said rows of memory cells, an averaging circuit () with inputs coupled to a plurality of said bit line conductors () and being arranged to determine an average level on respective analog signal levels on said plurality of bit line conductors (), a monitoring circuit () coupled to said averaging circuit () and being arranged to monitor said average level and to output a refresh command when said average level shows a predetermined behavior, and a refresh circuit () coupled to said monitoring circuit () and being arranged to refresh at least a selection of said plurality of memory cells () in response to said refresh command.

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Waalre, Netherlands

Victor M G Van Acht