Gatefield Corporation

Victor Levchenko

Jack Zezhong Peng

Kyung Joon Han

Robert M Salter, Iii

Robert U Broze

Volker Hecht

Robert V Broze

Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected through a buried bitline in juxtaposition with the switch transistor and the sense transistor over which are the floating gate and the control gate. The sense transistor can be fabricated simultaneously with fabrication of the switch transistor whereby the two transistors are identical in dopant concentrations.

Nonvolatile reprogrammable interconnect cell with programmable buried

The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V.sub.T of the access transistor formed by the control gate and the P- surface, and of the space charge region formed by the P substrate and the N+ drain of the EPROM cell.

Floating gate FPGA cell with counter-doped select device

Disclosed is a FPGA cell and array structure which use FN tunneling for program and erase. Each cell comprises a switch floating gate field effect transistor and a sense floating gate field effect transistor with the floating gates being common and the control gates being common. Programming of a cell is effected by voltage biasing the common control gate line and the source/drains of the sense transistor.

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San Francisco, CA, United States of America

Victor Levchenko