Tektronix, Inc.

Avnera Corporation

Other

Victor Lee Hansen

Samuel J Peters, Ii

Eric P Etheridge

Alexander C Stange

Charles L Saxe

Erik Landerholm

Shiv K Balakrishnan

A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a 'toothless' clock signal, wherein the sample counter is configured to be decremented by the 'toothless' clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the &#x201c;toothless&#x201d; clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.

SPDIF clock and data recovery with sample rate converter

A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a 'toothless' clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the 'toothless' clock signal to the sample rate converter.

A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.

A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Data transmission error reduction via automatic data sampling timing adjustment

A method for calibrating an instrument includes maintaining typical response values at respective frequency locations. The response of the instrument being calibrated is measured at a subset of frequency locations in the typical response. Response values for frequency locations not in the subset are estimated from the typical and measured response values. The instrument is calibrated based on the actual and estimated response values. Apparatus for calibrating an instrument includes a signal generator, coupled to the instrument, which generates a signal having known characteristics. A controller, coupled to the instrument, generates a calibration signal. Controller memory stores typical response values at respective frequency locations, and measures response values at a subset of the frequency locations. Response values for frequency locations not in the subset are estimated from the typical and measured response values. The instrument is calibrated in response to the measured and estimated response values.

Method and apparatus for calibrating an instrument

An improved sub-range ADC uses a sigma delta converter which eliminates both the sample and hold and digital-to-analog converter circuits of prior sub-ranging ADCs. An input analog signal is applied to a sigma delta modulator that provides a one-bit output. The one-bit output is input to a first analog filter and a digital correction circuit. The output from the first analog filter and the input analog signal, suitably delayed and optionally filtered, are input to a difference amplifier that provides the input to an ADC. The output of the ADC also is input to the digital correction circuit. The digital correction circuit includes a digital decimation filter for the one-bit sigma delta modulator output to produce a multi-bit digital output that is added to, the output from the ADC. The resulting digital signal may be additionally digitally filtered to produce a converted digital signal that corresponds to the input analog signal.

Sub-ranging analog-to-digital converter using a sigma delta converter

A method and apparatus for measuring the RMS value of an electrical signal. An electrical signal is converted to a digital signal. The digital signal is squared and low pass filtered to extract the DC component, the DC component being recognized as the mean-square of the signal. In use in a measurement device, the square root of the DC component is taken and displayed as the RMS value of the electrical signal.

Method and apparatus for measuring the mean square value of an

In a cascaded system of finite-duration impulse response filters, the transfer function of each filter relating its output data sequence to its input data sequence is selected such that elements of its output data sequence are in phase with the first element of its input data sequence. Operation of each filter other than the first cascaded filter is suppressed until it receives from the preceding filter, the first output data sequence element which is in phase with the first element of the input data sequence of the preceding stage, thereby ensuring that the first element of the output data sequence of the first filter is in phase with the first element of the input sequence to the first filter.

Phase coordinated multistage digital filter

A multistage digital filter for producing an output data sequence in response to elements of an input data sequence includes a multiplier for multiplying elements of the input data sequence by selected coefficients to produce product terms. An accumulator sums product terms to produce elements of a first filter stage output sequence and elements of the first filter stage output sequence are sequentially fed back to the multiplier. The multiplier and accumulator produce accumulated sums in response to the first stage output sequence to provide a second filter stage output sequence. In a similar fashion, each filter stage output sequence is fed back to the multiplier as the input sequence to the next filter stage until the output sequence of the last filter stage is produced.

Programmable multistage digital filter

A digital bandpass oscilloscope permits an operator to observe both time and frequency domain plots of analog signal components of frequency within a passband of selected center frequency during a time window of selected duration. The input signal is digitized, and the resulting digital data sequence is bandpass filtered and decimated by an adjustable decimation ratio to produce stored waveform data indicating the time dependent behavior of the passband during the time window. The oscilloscope, which utilizes the waveform data to produce both time and frequency domain displays of the passband, adjusts the decimation ratio to ensure that the number of data elements in the waveform data sequence is constant regardless of the selected duration of the time window and adjusts the bandwidth of the passband to minimize aliasing in the time domain display.

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Portland, OR, United States of America

Victor Lee Hansen