Intel Corporation

Inter Corporation

Victor Lau

Pak-Lung Seto

Nai-Chih Chang

Naichih Chang

William R Halleck

Gary Tsao

Suresh Chemudupati

Pak-Iung Seto

Eric J DeHaemer

Tracey L Gustafson

Kiran Vemula

Luke L Chang

Vicky P Duerk

Naichih (Neil) Chang

Bruno DiPlacido

Ankit Parikh

According to one embodiment of the invention, a method comprises measuring memory access latency for a prefetch cycle associated with a transmission of data from a memory device to a destination device such as a storage device. Hereafter, the prefetch rate is dynamically adjusted based on the measured memory access latency.

System and method for dynamic data prefetching

An embodiment of the present invention is a technique to process a plurality of I/O sequences associated with a storage device. A task context pre-fetch engine pre-fetches a task context from a task context memory based on a pre-fetch request. At least a multi-threaded transmit transport layer (T&#xd7;TL) processes the plurality of I/O sequences from an I/O pool simultaneously. The multi-threaded T&#xd7;TL generates the pre-fetch request and one or more frames from the plurality of I/O sequences. A switch fabric and controller routes the frame to a link layer associated with the storage device.

Multi-threaded transmit transport engine for storage devices

Methods of scheduling tasks in computer systems architectures are disclosed. In one aspect, a method may include comparing a connection address of a first node with a connection address of a second node, determining that the connection address of the first node matches the connection address of the second node, and scheduling tasks to the first and second nodes based, at least in part, on the determination. Apparatus to implement task scheduling, and systems including the apparatus are also disclosed.

Task scheduling to devices with same connection address

A method, computer program product, system (including a circuit card), and integrated circuit for initializing a buffer pool, such that the buffer pool includes a plurality of data buffers available for use during a plurality of I/O transfers. In response to the initiation of a first I/O transfer concerning a first data portion being transferred from a first data source to a first data target, the first data portion is written to a first portion of the plurality of data buffers. The first data portion is transferred to the first data target, and the first portion of the plurality of data buffers is released back to the buffer pool for use during one or more subsequent I/O transfers.

Dynamic memory buffer allocation method and system

According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.

Method using port task scheduler

In one aspect, a shared transport layer frame information structure (FIS) generation logic may generate FISes for each of a plurality of SATA ports. In a further aspect, a port addressing logic, in communication with the shared transport layer FIS generation logic, may select one of the SATA ports for each of the FISes.

Serial ATA port addressing

Methods and apparatus for host-side Serial ATA Native Command Queuing (NCQ) tag management are disclosed. In one aspect, an exemplary apparatus may include a memory and an NCQ tag selection circuit in communication with the memory. The memory may store information for each of a plurality of different NCQ tag values. The information for each NCQ tag value may indicate whether or not a command having the NCQ tag value has been issued. The NCQ tag selection circuit may examine the information in the memory, and may select an NCQ tag value having information that indicates that a command having the NCQ tag value has not been issued. Systems and architectures including such apparatus are also disclosed.

Hardware oriented host-side native command queuing tag management

A device includes a task context controller, at least one transport engine connected to the task context controller, and at least one comparator connected to the transport engine. The comparator to compare a data offset from a receive frame with a current data offset and a result is used to determine frame processing order.

Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications

Methods and apparatus for target-side SATA NCQ tag management are disclosed. In one aspect, an apparatus may include a status memory and a status manager circuit in communication with the status memory. The status memory may store status information for each of a plurality of commands that have been queued according to Native Command Queuing (NCQ). The status information may indicate whether or not each of the commands has been completed. The status manager circuit may generate and provide a status signal based on the status information stored in the status memory. Systems including such an apparatus and other components, such as hard disks, are also disclosed.

Hardware oriented target-side native command queuing tag management

An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.

Data buffer management in a resource limited environment

A method and apparatus for managing task context are provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.

Task context direct indexing in a protocol engine

A storage device is disclosed. The storage device includes a storage controller. The storage controller includes a direct memory access (DMA) Descriptor Manager (DM) to generate DMA descriptors by monitoring user data and a data integrity field (DIF) transferred between a host memory and a local memory based upon a function being performed.

DMA descriptor management mechanism

According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.

Command scheduling and affiliation management for serial attached storage devices

According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.

Mechanism to handle uncorrectable write data errors

A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.

Growing community of inventors

Marlboro, MA, United States of America

Victor Lau