Dell USA L P

Victor K Pecone

Jay R Lory

Craig S Jones

Deepak N Swamy

Kenneth L Jeffries

James Don Curlee

Russell Conley Smith

N Deepak Swamy

Kevin Lee Miller

Joseph A Vivio

Arthur Lopez

Darrell J Slupek

Nathan Wiscombe

A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.

Multiple bus system bus arbitration according to type of transaction

A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

System and method for accessing peripheral devices on a non-functional

A PCI bus master which determines the termination characteristics of one or more PCI targets coupled to the bus and uses this information to eliminate the wait states that are incurred during a bus cycle when a target device attempts to perform a data phase termination. According to the present invention, at initialization the bus master performs burst cycles on arbitrary address boundaries and stores the target's termination boundaries and cycle conditions. The bus master uses this information during burst transfers to initiate the data phase termination prior to the target, thus preempting the target from performing this termination. This operates to maintain the target's maximum burst capabilities while also eliminating the rearbitration wait states incurred when the bus master receives a termination from the target device. This also allows the bus master to chain together fast back-to-back PCI cycles while retaining bus ownership.

System for preemptive bus master termination by determining termination

A SCSI controller card which includes a standard SCSI connector that can support either one or two SCSI channels, as desired. The connector can receive either a standard single channel cable or a specially designed dual channel 'Y' cable to provide either one or two SCSI channels, respectively. The SCSI controller card includes logic that determines which cable is installed and switching logic which routes one or two SCSI channels to the connector accordingly. In the preferred embodiment, the SCSI adapter card includes two SCSI controllers which provide two SCSI channels. A first channel is connected directly to pins on the SCSI connector. A second channel is connected to switching logic, and a plurality of ground signals are also connected to the switching logic. The second channel is switched into the SCSI connector if the dual channel 'Y' cable is attached to the connector, and the ground signals are switched into the SCSI connector if the 'Y' cable is not detected. The SCSI adapter card continuously auto-senses which cable is installed at power-up, i.e., whether the dual channel 'Y' cable is installed or a standard single channel cable is installed, and switches in either the second channel or ground signals accordingly. Thus the present invention provides increased connectivity from a single connector as well as modular and upgradable SCSI bus routing options. The single external SCSI connector is mechanically compliant with the SCSI standard, but allows external routing of either one or two SCSI channels.

SCSI connector and Y cable configuration which selectively provides

A bus system is disclosed which includes first and second buses are coupled via an bus switch. The bus switch may be selectively turned on and off thus allowing the bus system to be electronically configured in a plurality of different configurations.

Adaptive expansion bus

A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.

Local proactive hot swap request/acknowledge system

An apparatus and method for address pipelining of a computer system that reduce the average number of wait states required to access a dynamic random access memory (DRAM) subsystem. A memory controller addresses a plurality of random access memory integrated circuits in pages of addresses wherein contiguous address pages are in different ones of the plurality of dynamic random access memory integrated circuits. Transparent latches associated with each of the different ones of the plurality of dynamic random access memory integrated circuits allow pipelining of address setups for more than one memory page at substantially the same time. The apparatus and method improve the write access times of a computer system and, when used with a computer system having address pipelining, both read and write accesses are improved because address set up latency time is reduced.

Apparatus and method for address pipelining of dynamic random access

A SCSI adapter card which provides one or more internal SCSI channels and includes connectors for an optional daughter card which provides an external SCSI connector. The daughter card is a parallel mezzanine style daughter board which provides modular and upgradable SCSI bus routing options. In the preferred embodiment, the adapter card includes two SCSI controllers which provide two internal SCSI channels. The daughter board can include up to 2 SCSI controllers for additional SCSI channels. The daughter board can reroute one or more of the internal SCSI channels to the external connector according to various SCSI routing options or can include one or more SCSI controllers for additional SCSI channels. In one embodiment, the daughter board does not include a SCSI controller, but rather serves to reroute one or more of the internal SCSI controllers to the external connector. In a second embodiment, the daughter board includes one or more SCSI controllers which provide external SCSI channels in addition to the internal SCSI channels. The incorporation of the external SCSI connector on the daughter board eliminates the need for the base PWA add-in card to include the external SCSI connector and also eliminates the requirement for internal 'umbilical' cables which burden mechanical limitations, decrease the reliability and complicate manufacturing and service.

Computer system SCSI adapter card including an add-in daughter board

A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.

Decoupled DMA transfer list storage technique for a peripheral resource

A computer is provided with a redundant power supply system using a plurality of power supply boxes having generally conventional, off-the-shelf configurations. The computer includes a housing having a wall opening spaced apart from and facing the side of a paralleling type circuit board having mounted thereon a plurality of AC electrical connectors and a spaced plurality of DC electrical connectors. The power supply boxes are mounted on carrier structures slidably received in the computer housing for drawer-like movement through the housing wall opening toward and away from the circuit boards. Each power supply box has an external wire bundle with blind mate DC electrical connectors mounted on the outer ends of its leads and supported by the carrier structure for mating connection with their associated circuit board connectors when the carrier structure is moved into adjacency with its associated circuit board. The carrier structure also supports an AC connector structure which is mated with its associated circuit board connector in response to such movement of the carrier structure. A switch carded by each carrier structure is operative to selectively enable and disable its associated power supply box and releasably lock the carrier structure to the computer housing.

Computer power supply apparatus

A daughter card for mounting to an adapter card, wherein the daughter card includes adapter card connectors for mounting to the adapter card and also an edge connector for insertion directly into a computer slot so that the daughter card may also function as a stand-alone card. The daughter card is both mechanically and electrically compliant as an independent PCI add-in card and includes a PCI edge connector for insertion directly into a PCI slot. This provides additional modularity since the daughter card can be purchased and configured as a separate and independent PCI adapter card as well as for mating to a host adapter card to provide extra functionality to the host adapter card. In addition, since the daughter card can be directly inserted into the PCI bus, the daughter card provides greater component access and probing for testing. Further, the daughter card can be tested independently of the host adapter card during manufacturing functional test, thus providing more reliable testing.

Computer system modular add-in daughter card for an adapter card which

A personal computer system utilizes a simplified motherboard having connectors on the motherboard that are electrically connected to data, address, control, power and ground signals necessary for expansion and upgrade of the computer system and a riser card or cards having the desired interface connectors and logic circuits thereon. The present invention provides for operatively and removably coupling a plurality of I/O expansion cards, host local bus interfaces and future system upgrades for the computer system without burdening the base cost thereof. The computer system may be expanded or upgraded at any time during manufacture or in the field. A simple and low cost common motherboard is utilized in the manufacture of the computer systems, resulting in lower manufacturing costs. A base computer system may be easily upgraded when more features are desired. A riser card is configured for the desired features, plugged into the motherboard connectors, and the desired new peripheral features plugged into the riser card to complete the upgrade.

Modular host local expansion upgrade

A leadless high density connector including a plurality of connector pins each having multiconductor pins electrically connected to solder balls on the back side of the connector for interconnection to a PWB. The solder balls form a ball grid array (BGA), which replaces thin gull wing leads used on connectors of prior art. The use of BGA technology as applied to high density connectors provides a plurality of benefits associated with BGA technology. The signal carrying capacity of the connector is increased since the bottom surface of the connector is available for interconnecting signal paths rather than being limited to the peripheral edges as common for leaded packages. The resulting profile of the connector is substantially reduced allowing increased component and wiring density. The resulting bond strength using BGA technology is greater than that with a leaded equivalent due to the increased bond surface area and resulting anchoring effect. Therefore, BGA technology allows significantly increased yields over connectors using leads as known in prior art. The electrical characteristics of a connector according to the present invention is substantially improved since the inductance per pin is reduced using BGA as compared to leads. In this manner, connectors according to the present invention are more suitable for high speed applications especially when combined with the ability to interleave ground and signal connections.

Leadless high density connector

An apparatus and method for a computer system that selectively disables expansion peripheral interface devices so that they do not interfere with diagnostic testing of related computer system peripheral interface devices. The present invention selectively disables the peripheral interface devices by control of the clock signals thereto. The clock signals may be selectively controlled by means of a software test program that may also be used to automate the diagnostic testing of the computer system. In addition, the computer system may be remotely tested and diagnosed because the present invention makes it unnecessary for the physical removal of devices that may cause false signal responses during the diagnostic tests.

Growing community of inventors

Austin, TX, United States of America

Victor K Pecone