Bell Telephone Laboratories

Victor K Huang

Donald E Blahut

Masakazu Shoji

Charles M Lee

Richard L Townsend, Jr

Jonathan A Fields

Richard L Ruth

A single-chip processor architecture is disclosed which permits the registers and control latches of the processor to be easily accessed without using instructions to achieve such access. The architecture provides for an internal access (IA) function which is enabled by applying an IA Request signal to an IA terminal of the processor. During the IA function, program execution in the processor is suspended and the registers and control latches may be accessed as if they were storage locations in a random access memory. After the IA function is enabled, the address of a register or control latch selected for access is applied to the Address/Data port of the processor, and an IA Control Code specifying the strobing of the Address/Data port is applied to the Status terminals of the processor. After strobing of the address, a second IA Control Code specifying either reading or writing of the selected register or control latch is applied to the Status terminals. If the second Control Code specifies reading, the contents of the selected register or control latch is provided at the Address/Data port. If the second Control Code specifies writing, data received at the Address/Data port is stored in the selected register. The IA function facilitates program development in the processor because it provides an efficient means for observing the internal machine states and register contents of the processor. Functional testing of the processor is also facilitated because the IA function increases the availability of the internal nodes of the processor chip for the application of test signals and for the observation of circuit responses.

Microprocessor architecture having internal access means

A microcomputer system arranged for performing direct memory access operations has direct memory access circuitry included on a single chip with the main processor of the microcomputer. Addressing for direct memory access operations is accomplished by circuitry also used for generating addresses when processing routine instructions in the main processor.

Microcomputer arranged for direct memory access

A sequential address generation arrangement (45, 61, 62, 99, 102) generates a sequence of addresses in response to an initial address and disables generation of the sequence of addresses in response to a control signal (LAST NIB) produced from at least a portion of the initial address at the conclusion of generation of a predetermined number of sequential addresses, the predetermined number being decoded from the initial address.

Special address generation arrangement

A Central Processing Unit (CPU) includes a hardware op-code extending register (OER) for storing a code for programmable selection of optional CPU features which modify processor operations defined by the op-code in each instruction. A control section in the CPU decodes both the op-code of a current instruction and the code in the OER, effectively combining the two to form an extended op-code capable of defining a larger set of processor operations than the op-code carried in each instruction. The code in the OER is changed only when the CPU executes an instruction for transferring a new code into OER. Thus the code in OER can remain stationary over many instruction cycles.

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Scotch Plains, NJ, United States of America

Victor K Huang