Texas Instruments Corporation

Victor Ivanov

Jozef C Mitros

Weidong Tian

Pinghai Hao

Semiconductor devices and fabrication methods are provided in which a capacitor dielectric is provided with phosphorus or other n-type dopants through implantation of other techniques to reduce the voltage coefficient of capacitance and/or the dielectric absorption of the capacitor.

Methods for reducing capacitor dielectric absorption and voltage coefficient

The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

Memory device with reduced cell area

Methods fabricate DEMOS devices having varied channel lengths and substantially similar threshold voltages. A threshold voltage is selected for first and second devices. First and second well regions are formed. First and second drain extension regions are formed within the well regions. First and second back gate regions are formed within the well regions according to the selected threshold voltage. First and second gate structures are formed over the first and second well regions having varied channel lengths. A first source region is formed in the first back gate region and a first drain region is formed in the first drain extension region. A second source region is formed in the second back gate region and a second drain region is formed in the drain extension region.

Methods of performance improvement of HVMOS devices

The present invention provides a semiconductor device (), a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the semiconductor device () includes a floating gate () located over a semiconductor substrate (), wherein the floating gate () has a metal control gate () located thereover. The semiconductor device (), in the same embodiment, further includes a dielectric layer () located between the floating gateand the metal control gate (), the dielectric layer () having a gettering material located therein.

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Richardson, TX, United States of America

Victor Ivanov