Huawei Technologies Co., Limited

Victor Gissin

Tao Li

Xin Qiu

Junying Li

Guanfeng Zhou

Jiashu Lin

Haitao Guo

Huawei Liu

Chunyi Tan

Huifeng Xu

Pei Wu

Shengwen Lu

Hongguang Liu

Huichun Qu

Jinbin Zhang

Haixin Yu

A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by an NVMe storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

Data processing method and NVMe storage device

A method, device, and system for controlling a data read/write command in an NVMe over fabric architecture. In the method provided in the embodiments of the present disclosure, a data processing unit receives a control command sent by a control device, the data processing unit divides a storage space of a buffer unit into at least two storage spaces according to the control command sent by the control device, and establishes a correspondence between the at least two storage spaces and command queues, and after receiving a first data read/write command that is in a first command queue and that is sent by the control device, the data processing unit buffers, in a storage space that is of the buffer unit and that is corresponding to the first command queue, data to be transmitted according to the first data read/write command.

Method, device, and system for controlling data read/write command in NVMe over fabric architecture

A data processing method and system, where the method includes: receiving, by a non-volatile memory express (NVMe) controller, a first Peripheral Component Interconnect express (PCIe) packet sent by a host, where a memory in the NVMe controller is provided with at least one input/output (I/O) submission queue, and the first PCIe packet includes entrance information of a target I/O submission queue and at least one submission queue entry (SQE); and storing the at least one SQE in the target I/O submission queue based on the entrance information of the target I/O submission queue. Therefore, an NVMe data processing process is simplified and less time-consuming, and data processing efficiency is improved.

Non-volatile memory express (NVMe) data processing method and system

In an NVMe-based storage system, a host is connected to an NVMe controller through a PCIe bus, and the NVMe controller is connected to a storage medium. The NVMe controller receives from the host a data packet that carries payload data and an association identifier. The association identifier associates the payload data with a write instruction. The NVMe controller obtains the write instruction according to the association identifier, and then writes the payload data into the storage medium according to the write instruction.

NVMe-based data writing method, apparatus, and system

A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

NVMe-based data read method, apparatus, and system

Non-volatile memory (NVM) express (NVMe) data processing method and system

A control device for a non-volatile memory express (NVMe) over fabric architecture is provided. The control device comprises a network adapter and a processor coupled to the network adapter by a bus. Data is transmitted between the control device and a storage device in the NVMe over fabric architecture. The processor is configured to obtain an available storage space of the storage device, determine whether a storage space required by a first data to be transmitted according to a first data read/write command is equal to or less than the available storage space, and send the first data read/write command to the storage device if the storage space required by the first data is equal or less than to the available storage space and suspend sending of the first data read/write command if the storage space occupied by the first data is greater than the available storage space.

Method, device, and system for buffering data for read/write commands in NVME over fabric architecture

A data processing method and a storage apparatus are disclosed. The data processing method includes: receiving, by a non-volatile memory express (NVMe) storage device, an NVMe write command sent by a host, where the NVMe write command carries a key and a value pointer, the value pointer points to first storage space, and the first storage space is used to store a value; obtaining, by the NVMe storage device, the key from the NVMe write command and a value length, and allocating second storage space to the value according to the value length, where the second storage space is in the NVMe storage device; and obtaining, by the NVMe storage device, the value from the host, and storing the value in the second storage space.

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Shenzhen, China

Victor Gissin