Advanced Micro Devices Corporation

Victor F Andrade

Kelly M Horton

Randal L Posey

Michael C Braganza

Saba Rahman

James R MacDonald

Douglas D Gephardt

Jerry D Moench

Dan S Mudgett

Michael K Ciraula

Floyd L Dankert

Michael Bienek

Alexander W Schaefer

Amy M Novak

Soolin Kao Chrudimsky

Jan Michael Huber

Gerard T McKee

Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Method and apparatus to achieve more level thermal gradient

A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.

Memory array with global bitline domino read/write scheme

An integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory (DRAM) banks during idle memory cycles. The refresh queue logic includes a queue counter and allows the refresh requests to be given a lower priority than other memory transactions until the required refresh rate is in danger of being violated. At this lower priority the refresh requests are honored and retired from a refresh queue only in the absence of other memory transactions. In the event that the refresh queue becomes full, top priority is given to the execution of a refresh request. In this case, a refresh request is honored and retired from the queue immediately after the conclusion of the current memory transaction. This queuing mechanism allows the refresh requests to be buffered until idle memory cycles are available or until absolutely necessary to prevent the violation of refresh timing constraints.

Integrated processor and memory control unit including refresh queue

An integrated processor is provided that employs an improved address decoding method during bus cycles of an external master. An external PCI master may initiate a cycle (either memory or I/O) on the PCI bus by asserting an address signal on the PCI bus along with the FRAME signal which indicates the start of the PCI cycle. After the address becomes stable, the bus interface unit transfers the address signal to the CPU local bus. The bus interface unit does not assert or drive the address strobe signal ADS at this time, however, and thus a CPU local bus cycle is not initiated. The decode logic within the memory or I/O control unit responsively decodes the address signal to determine whether the address is mapped within the address space of the respective control unit. If the address is not within the mapped space of the respective control unit, the control unit does not assert the hit signal, and thus the bus interface unit does not initiate a corresponding CPU local bus cycle and does not drive the PCI device select signal DEVSEL. The PCI bus cycle may then proceed normally in that either another PCI slave may assert the device select DEVSEL signal to indicate that it is responding to the cycle, or the cycle will be aborted by the PCI master. If the address is determined to be within the mapped space of the respective control unit, the control unit asserts the hit signal to inform the bus interface unit that the address is mapped to a device situated on the CPU local bus. The bus interface unit accordingly asserts the device select signal DEVSEL to claim the current cycle, and initiates a corresponding cycle, memory or I/O cycle, or the CPU local bus.

Computer system employing a control signal indicative of whether address

A computer system is disclosed for selectively invalidating the contents of cache memory in response to the removal, modification, or disabling of system resources, such as for example, an external memory device. The computer system includes an interface unit which defines an address window for the particular system resource. The address window is implemented through the use of a lower address register and an upper address register, which are loaded in response to a lower and upper enable address signal. An upper comparator compares each tag address with the upper address register value, and a lower comparator compares each tag address with the lower address register value. If the tag address falls within the window, it is flushed by the generation of appropriate control signal. In an alternative embodiment, the present invention can be implemented through software by instructions in microcode. As yet another alternative, the present invention can be implemented by comparing each memory window address value with the stored tag address in the cache.

System and apparatus for partially flushing cache memory

A system is disclosed for optimizing data transfer times between an external Master device and main memory. The system includes an integrated processor with a PCI bridge for orchestrating data transfers with the PCI Master over the PCI bus, and a memory controller for controlling access to the main memory. During burst cycles of the PCI Master, the PCI bridge expedites data transfers by providing the memory address to the memory controller early during periods when the PCI Master is slow in transmitting or receiving data. When the PCI Master is unable to respond in a timely fashion, and while the PCI bridge is in control of the local bus, the PCI bridge asserts a MEMWAIT signal to the memory controller to indicate the need to throttle down a data transfer. At substantially the same time, the PCI bridge supplies the memory controller with the next memory address to enable the memory controller to open the appropriate page (and/or precharge the last page) in the memory to expedite subsequent data transfers by asserting (and/or deactivating) the proper row address strobe (RAS) lines. When MEMWAIT is deasserted by the PCI bridge, the memory controller immediately responds by asserting the column address strobe to drive in or drive out the data. As a result of opening the page in memory early, the system potentially saves the RAS access time (t.sub.RAC) and the RAS precharge time (t.sub.RP) in the data transfer.

Prepaging during PCI master initiated wait cycles

A system is disclosed for minimizing delays for critical timing parameters during DRAM transactions. The present invention comprises a modified memory control unit which includes a programmable DRAM edge generator for increasing the resolution times for assertion of DRAM control signals that operates using both edges of the memory clock. The memory control unit (or MCU) includes configuration registers that are configured during system initialization by the BIOS to set desired delay times for critical DRAM timing parameters, such as assertion of the row address strobe (RAS) signal, the assertion of the column address strobe (CAS) signal, and the timing of the switch from the row address to the column address. The DRAM edge generator includes shifter delay circuits that control the timing of the control signals based upon the status of the configuration registers. The shifter delay circuits also receives an enable signal from the DRAM controller, a precharge signal from a bank precharge counter, and bank and byte select signals from the DRAM address router.

Memory control unit with programmable edge generator to minimize delay

A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external 'debug' interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code. If, however, the SMM interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts an ICE interrupt signal which causes the microprocessor core to commence executing the SMM code. Both the SMM code and ICE code may be mapped within a region of system memory which is common to the mapping of a video controller.

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Austin, TX, United States of America

Victor F Andrade