Intel Corporation

Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel IP Corporation

Victor Da Fonte Dias

Giuseppe Li Puma

Zdravko Boos

Thomas Mayer

Roberta Burger-Riccio

Florian Hus

Olaf Ströble

An apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal is provided. The in-phase signal and the quadrature signal are based on a radio frequency receive signal. The apparatus includes an imbalance estimation module configured to generate a first correction signal related to a first phase shift, and to generate a second correction signal related to a second phase shift. Further, the apparatus includes a first digital-to-time converter configured to receive the first correction signal and a local oscillator signal. The first digital-to-time converter is further configured to supply a first replica of the local oscillator signal for a first mixer generating the in-phase signal, wherein the first replica of the local oscillator signal has the first phase shift with respect to the local oscillator signal. The apparatus further includes a second digital-to-time converter configured to receive the second correction signal and the local oscillator signal. The second digital-to-time converter is further configured to supply a second replica of the local oscillator signal for a second mixer generating the quadrature signal, wherein the second replica of the local oscillator signal has the second phase shift with respect to the local oscillator signal.

Apparatus for reducing an amplitude imbalance and a phase imbalance between an in-phase signal and a quadrature signal

One embodiment covers an apparatus for generating a transmission signal. The apparatus may include a signal generator that generates a first signal with a first frequency spectrum comprising a carrier frequency; a power control unit that provides a power information signal which represents a signal level of the transmission signal residing at the carrier frequency; a first signal shaper for noise-shaping the first signal based on the power information signal to form a second signal which has a noise component in at least one frequency range remote from the carrier frequency, the noise component of the second signal being from one or more signal components associated with the carrier frequency; and a signal output that provides the second signal in the form of a transmission signal.

Generation of a transmission signal

A transmitter includes estimation circuitry and correction circuitry. The estimation circuitry is configured to estimate, based at least on a phase error between a local oscillator and a reference frequency, values for parameters that describe a frequency deviation experienced by a phase locked loop (PLL) during transmission of the data sample, wherein the PLL includes a local oscillator. The correction circuitry is configured to generate a correction term based at least on the estimated parameters; adjust the data sample with the correction term to generate a compensated data sample; and provide the compensated data sample for modulation of a carrier wave generated by the local oscillator.

Direct compensation of IQ samples for undesired frequency deviation in phase locked loops

A transmitter comprising a phase computation circuit configured to receive a complex baseband signal comprising an in-phase signal and a quadrature signal forming an I-Q data pair, and determine a first rotation angle and a second rotation angle based on the I-Q data pair. The transmitter further comprises a modulation circuit coupled to the phase computation circuit configured to determine a three-level modulated waveform having a lower negative level, a zero level and a higher positive level, based on the first rotation angle and the second rotation angle; and generate the three-level modulated waveform based on the determination.

Transmitter (TX) dead-time modulation

Techniques for generating signals based on two constant amplitude phasors are discussed. One example apparatus includes phase calculation circuitry that generates first and second angles from a representation of a complex signal; distributor circuitry that receives the second angle and outputs a positive and a negative version of it; a first signal generator configured that receives the first angle and one of the positive or the negative version and generates a first signal based on the first angle and the one of the positive or the negative version; a second signal generator that receives the first angle and the other of the positive or the negative version and generates a second signal based on the first angle and the other of the positive or the negative version; and a combiner that combines the first and the second signal and generates an output signal equivalent to the complex signal.

Transmit amplitude and phase modulation based on two constant-amplitude phasors

A hybrid polar I-Q transmitter comprises an I-Q quantization circuit configured to receive an in-phase signal and a quadrature signal forming a first I-Q data pair, and generate a quantized in-phase signal and a quantized quadrature signal forming a second I-Q data pair, respectively, based on a resolution information of a digital-to-analog converter (DAC). Each of the first and second I-Q data pairs corresponds to a point in an I-Q constellation diagram comprising an I axis and a Q axis that are orthogonal to one another. The transmitter further comprises a quantization reduction circuit configured to determine a first rotation angle and a second rotation angle of the I-axis and Q-axis, respectively, based on the first I-Q data pair and the second I-Q data pair, and use the determined first rotation angle and the second rotation angle for generating an RF output signal.

Hybrid I-Q polar transmitter with quadrature local oscillator (LO) phase correction

A hybrid polar I-Q transmitter includes an I-Q derivation circuit configured to receive a first and second I-Q data components comprising a first I-Q data pair, and generate a first and second I-Q derived data components comprising a second I-Q data pair, respectively, based thereon, by utilizing a resolution information of a digital-to-analog converter (DAC) and a design criteria. The I-Q derivation circuit is further configured to determine a residual angle corresponding to a phase angle difference between the first I-Q data pair and the second I-Q data pair. The hybrid polar I-Q transmitter further comprises a modulation circuit configured to compensate the determined residual angle corresponding to the phase angle difference between the first I-Q data pair and the second I-Q data pair.

Hybrid I/Q and polar transmitter

A signal processing apparatus is described comprising a sampling time control circuit configured to provide a sequence of digital values, each digital value specifying a sampling time of a sequence of sampling times, a sampling circuit configured to sample an input signal according to the sequence of sampling times to generate a sampling value of the input signal for each sampling time of the sequence of sampling times and a processing circuit configured to receive the sampling values and configured to process the sampling values based on the sampling times, wherein the sampling time control circuit is configured to introduce jitter into the sampling times, by varying the time intervals between adjacent sampling times.

Signal processing apparatus and method for processing a signal

A shunt regulator for stepping down an input potential to an output potential, has an input for applying the input potential, an output for tapping off the output potential and a voltage drop circuit, across which the voltage difference between the input potential and the output potential drops. It is possible for the current flowing through the voltage drop circuit or its lower and/or upper limit value to be adjusted.

Shunt regulator

The circuit arrangement includes a first and a second input to supply a first and a second supply voltage and also an output. The circuit arrangement includes a first transistor, which is connected between the first input and the output, and a second transistor, which is connected between the second input and the output. The first and second transistors include a respective substrate connection coupled to a supply connection. In addition, the circuit arrangement includes a third and a fourth transistor, which are connected between the first input or the second input and the supply connection, and also a control circuit, which is coupled to the first and second inputs and to control connections of the first and second transistors.

Circuit arrangement for voltage selection, and method for operating a circuit arrangement for voltage selection

A method for converting an analog input signal into a digital value with successive approximation. A first comparison operation is provided before a first approximation, which subdivides a predefined input voltage interval into five partial intervals according to four reference potentials. During the comparison operation, a partial voltage interval determined is used in the ensuing approximation for the selection of a new reference potential pair to be used. This method enables higher sampling rates. At the same time, the range of the input signal is increased.

Method for converting an analog input signal, and analog-to-digital converter

The quantizer (') has an input network () which generates N different drive signals (V) as a function of the quantizer input signal (V&#x2212;V). The input network () is designed in such a way that a value of the respective drive signal (V) which is greater than a comparison value indicates that the quantization threshold which is associated with the respective drive signal (V) has been exceeded. Furthermore, the quantizer has a switching network (), which associates the N drive signals (V) with the N comparator inputs.

Quantizer in a multilevel sigma-delta analogue/digital converter

The invention provides a clocked analog/digital converter for successive approximation which is designed using a jointly used amplifier and a dynamic range expansion facility by means of a special design for the comparison circuit in the first converter stage. The comparison circuits in the analog/digital converter allow decisions to be made for the further signal processing previously in a preceding time period. Two respective generator circuits in successive converter stages share one amplifier. This reduces the amount of space taken up and current drawn, increases the clock rate and simplifies signal processing for signals with high levels.

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Neubiberg, Germany

Victor Da Fonte Dias