Texas Instruments Corporation

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Imec

Interuniversitair Microelektronica Centrum (imec)

Victor C Sutcliffe

Andrew Marshall

Karen Irma Maex

Gerald Beyer

Caroline Whelan

Jean Paul Gueneau De Mussy

Amitava Chatterjee

Howard L Tigelaar

Clyde R Fuller

One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Semiconductor interconnect

A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Method for selective deposition of a thin self-assembled monolayer

Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.

Methods for selective integration of airgaps and devices made by such methods

A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Extraction of interconnect parasitics

In one embodiment, the present invention provides a method of forming a dynamic random access memory device which utilizes self-aligned contact pads and for the bit line and storage node contacts. A transfer gate 14 is formed at the fact of a semiconductor region . The semiconductor includes a bit line contact region and storage node contact region adjacent opposite edges of the transfer gate . Transfer gate is surrounded with an insulating material . A conductive layer is formed over the transfer gate , over the bit line contact region and over the storage node contact region. This conductive layer is then etched so that a first portion of the conductive layer provides an electrical contact to the bit line contact region and a second portion of the conductive layer provides an electrical contact to the storage node contact region. The bit line and storage node electrode can then be formed in electrical contact with the first and second portions of the conductive layer and , respectively.

Method of forming a memory cell with self-aligned contacts

A sputter-etch process is used to etch vias having substantially vertical sidewalls, such that a sloped sidewall is formed. Using a silicon dioxide layer in which to form the vias, slopes of approximately 45.degree. may be obtained. A second insulator layer may be provided to protect the leads and other portions of the device during the sputter-etch to prevent damage.

Growing community of inventors

McKinney, TX, United States of America

Victor C Sutcliffe