Vlsi Technology, Inc.

Philips Electronics North America Corporation

Victor C Liang

Subhas Bothra

Harlan Lee Sur, Jr

Mark Rubin

Olivier F Laparra

Bijan Moslehi

An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.

Trench-diffusion corner rounding in a shallow-trench (STI) process

A method is presented in which nitrogen-based gas in incorporated in polysilicon gate re-oxidation to improve hot carrier performance. A gate oxide layer is formed. Gate material is deposited on the gate oxide layer. The gate material is etched to form a gate structure. The gate oxide layer and the gate are re-oxidized. During re-oxidation, nitrogen-based gas is introduced to nitridize re-oxidized portions of the gate oxide layer.

Incorporation of nitrogen-based gas in polysilicon gate re-oxidation to improve hot carrier performance

Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes exposing the semiconductor wafer to an electron dose that is configured to neutralize the positive charge that is built-up on the at least part of the second metallization layer. The neutralizing is thus configured to substantially prevent tungsten plug erosion.

Method for making reliable interconnect structures

Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded. In this manner, the positive charge that is built-up on the at least part of the second metallization layer is neutralized to prevent tungsten plug erosion.

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Milpitas, CA, United States of America

Victor C Liang