Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Victor Avila

Hua-Ling Cynthia Hsu

Henry Chin

Abhijeet Manohar

Tien-Chien Kuo

Fanglin Zhang

Jong Hak Yuh

John Randall

Hsing Heng Hsieh

An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

Nonvolatile memory with ongoing program read

A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

Burst programming of a NAND flash cell

Aspects of a storage device including a memory and a controller are provided for error detection and data integrity checking during the data transfer of write operations. The memory includes a write enable input. The controller generates data integrity information based on at least one data byte to be written to the memory, and transfers the at least one data byte and the data integrity information to the memory, with the data integrity information being transferred to the write enable input. A data integrity circuit receives the at least one data byte and the data integrity information from the controller, and detects whether an error exists in the at least one data byte based on the data integrity information. Accordingly, error detection of data being written to memory may be improved by the data integrity checking of the data prior to being written to the memory of the storage device.

Data integrity check for writing data in memory

A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

Growing community of inventors

San Jose, CA, United States of America

Victor Avila