General Electric Company

Harris Corporation

Electric Power Research Institute Incorporated

Intersil Corporation

Silicon Power Corporation

Intersil Americas Inc.

Victor A Temple

Homer H Glascock, Ii

Donald L Watrous

Constantine A Neugebauer

Stephen Daley Arthur

John M Neilson

James F Burgess

Dante E Piccone

Boris Reshetnyak

Francis J Kub

Karl D Hobart

Armand P Ferro

Carl Franklin Wheatley, Jr

Robert J Satriano

Frederick P Jones

Bantval J Baliga

Alexander J Yerman

Michael S Adler

Tat-Sing P Chow

James Kevin Azotea

Peter V Gray

B Jayant Baliga

Wirojana Tantraporn

Eric X Yang

Sabih Al-Marayati

Thomas R Peterson

Donald L Schaefer

A semiconductor switching device for switching high voltage and high current. The semiconductor switching device includes a control-triggered stage and one or more auto-triggered stages. The control-triggered stage includes a plurality of semiconductor switches, a breakover switch, a control switch, a turn-off circuit, and a capacitor. The control-triggered stage is connected in series to the one or more auto-triggered stages. Each auto-triggered stage includes a plurality of semiconductor switches connected in parallel, a breakover switch, and a capacitor. The control switch provides for selective turn-on of the control-triggered stage. When the control-triggered stage turns on, the capacitor of the control-triggered stage discharges into the gates of the plurality of semiconductor switches of the next highest stage to turn it on. Each auto-triggered stage turns on in a cascade fashion as the capacitor of the adjacent lower stage discharges or as the breakover switches of the auto-triggered stages turn on.

Matrix stages solid state ultrafast switch

A circuit for turning OFF a thyristor. The circuit includes at least one first circuit element configured to provide a high reverse turn-OFF voltage to the thyristor gate for a predetermined period of time. Immediately following the predetermined period of time, at least one second circuit element provides a normal reverse turn-OFF voltage to the thyristor gate. The normal reverse turn-OFF voltage is substantially lower than the high reverse turn-OFF voltage.

Device and method for controlling the turn-off of a solid state switch (SGTO)

Matrix-stages solid state ultrafast switch

One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions. The localized lifetime killing portion may comprise a plurality of laterally confined and laterally spaced apart lifetime killing regions. Another device may include one or more PN junctions.

Devices formable by low temperature direct bonding

A method for making at least one semiconductor power device with current conduction in a vertical direction from a plurality of semiconductor substrates includes processing at least one surface of each of two semiconductor substrates to form at least one of a metal layer and a doped region. The substrates are bonded together so that the at least one processed surface of each of the two semiconductor substrates define outer surfaces of the semiconductor device. The method further includes annealing the bonded together substrates at an anneal temperature so as to not adversely effect the processed surfaces. The method allows the making of a double sided semiconductor power device with a reduction in the number of sequential processing steps. The direct bonding approach allows current production recipes for fabricating single sided power devices to be used without requiring a separate process sequence.

Methods for making semiconductor devices by low temperature direct bonding

A hermetic thin pack semiconductor device. The semiconductor device has a semiconductor substrate and at least one electrode on the upper surface of the semiconductor substrate. A lid of a ceramic material for the semiconductor device has at least one opening extending through the lid. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the electrode and the third electrically conductive material and positioned on a corresponding portion of the electrode opposite a corresponding opening in the lid.

Hermetic thin pack semiconductor device

A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200 .mu.m. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer. An implanted region may be formed at a surface of the at least one substrate opposite the processed surface prior to bonding. The implanting may comprise implanting with a lifetime killing implant or a dopant. An epitaxial layer may be formed on the backside of a substrate. The step of processing may include forming a metal layer. Thus, the anneal temperature is preferably less than a temperature related to a characteristic of the metal layer. For an aluminum layer, the anneal temperature is preferably less than about 450.degree. C. If a barrier metal is used between the aluminum and substrate, the anneal temperature may be in a range of about 450 to 550.degree. C.

Advanced methods for making semiconductor devices by low temperature

A method of fabricating a MOS controlled thyristor (MCT) semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels. The method uses a single, dopant-opaque mask to form MCT structure above the bottom N and P layers, including the upper portions of PNP and NPN transistors which form the MCT and On-FETs and Off-FETs which operate the MCT. The single mask may also be used to fabricate floating field rings for the device. The method may also be used on both sides of the device to provide a Fast Turn Off (FTO) device with both On- and Off-FETs on one side and at least an Off-FET on the other side.

One mask, power semiconductor device fabrication process

A power pack including a power device and driver circuit sandwiched between a base plate and a lid. The base plate and lid having flat exterior surfaces for bonding with heat exchangers and/or an external bus to provide both two-sided cooling and two-sided electrical access. The driver circuit and power device are spaced apart to allow parallel and separate thermal conduction paths to both the base plate and lid. The power pack further including a seal enclosing the power device and driver circuit between the base plate and lid.

Flat power pack

A circuit and method of protecting the antiparallel diodes of a power bridge circuit from stress induced failures caused by the fast operation of the power switches. An auxiliary power switch is provided in parallel to the main power switch which is operable during the reverse recovery of the antiparallel diode, after which the main power switch carries the bulk of the switch current.

Protection device for solid state switched power electronics

An asymmetric snubber resistor in accordance with the present invention includes a cathode, an N+ region, an N- region, a plurality of P+ regions, and an anode. The N+ region is disposed over the cathode, the N- region is disposed over the N+ region, the plurality of P+ regions are disposed over the N- region, and the anode is disposed over the plurality of P+ regions and exposed portions of the N- region. The asymmetric snubber may also include N regions between the P+ regions. The asymmetric snubber resistor replaces the snubber diode and the snubber resistor in a typical snubber circuit.

Asymmetric snubber resistor

One embodiment of a metal oxide semiconductor controlled thyristor in accordance with the present invention has a semiconductor wafer with opposing first and second surfaces. The wafer includes first through sixth sequential regions which are disposed one above the other. The first region includes the second surface of the wafer and each of the second through sixth regions has at least a portion which extends up to the first surface. The first, third, and sixth regions have a first type of conductivity and the second, fourth, and fifth regions have a second type of conductivity. A trench with a bottom and sidewalls extends from the first surface and passes through the fourth, fifth, and sixth regions and into the third region. A dielectric material coats the bottom and sidewalls of the trench and a conductive material fills the remainder of the trench. In an alternative embodiment: the third through sixth regions have at least a portion which extends up to the first surface; the first, fourth, and sixth regions have a first type of conductivity; the second, third, and fifth regions have a second type of conductivity; and the trench extends from the first surface and passes through the fifth and sixth regions and into the fourth region.

Metal oxide semiconductor controlled thyristor with an on-field effect

A four-region semiconductor device (that is, a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.

Semiconductor device with improved turn-off capability

A method of processing wafers for power devices in which the wafer has a desired thickness less than the thickness necessary to provide mechanical support. A silicon wafer of the desired thickness is bonded to a carrier wafer until most, if not all, of the processing steps are completed, after which the silicon wafer is separated from its carrier wafer. The carrier wafer may serve as a diffusion source, and the areas of the bonding of the silicon wafer to the carrier wafer may be selected consistent with the devices or groups of devices to be formed by the separation of the two wafers. The carrier wafer may by bonded to the device wafer over nearly the full surface area and the carrier wafer remain a part of the final device.

Growing community of inventors

Clifton Park, NY, United States of America

Victor A Temple