Lsi Logic Corporation

Lsi Corporation

Victer K Chan

Emery O Sugasawara

Ronnie V Vasishta

A single multifunctional structure can be used to determine the alignment accuracy of the contact layer and the interconnect layer by inline visual inspection and by determination of the end of line electrical resistance properties.

Alignment of openings in semiconductor fabrication

A method for improving the accuracy of quiescent current testing by reducing reliance on absolute quiescent current test limits. Initially, the device under test is placed into a static DC state in a traditional manner. Quiescent current is then measured with the power supply to the device set to a nominal operating voltage. Next, a fixed voltage lower than the nominal power supply voltage is applied to the integrated circuit in order to reduce the quiescent current consumed by the device. An additional quiescent current measurement is taken. The difference in quiescent current between the first and second measurements is then calculated. Additional quiescent current measurement(s) are also taken at increasing lower supply voltages. The differences in quiescent currents between each of these measurements is also calculated. After a sufficient number of measurements have been gathered, the resulting difference values are examined to determine the &ldquo;linearity&rdquo; of the quiescent current reduction. In an acceptable device, the lower power supply voltages cause the leakage or quiescent current inherent in the integrated circuit to decrease in a roughly exponential manner. Therefore, if the reduction in quiescent current is roughly exponential, it is generally assumed that the detected quiescent currents are a result of normal transistor effects. If the change in currents approximates a linear function, however, it is likely that the device under test contains a defect and the device is rejected.

Reduced voltage quiescent current test methodology for integrated circuits

The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Method and system for alignment of openings in semiconductor fabrication

Circuitry for testing and comparing ESD protection structures is provided on a semiconductor integrated circuit. Analysis of charge transmitted to a test capacitor on board the chip provides for improved accuracy in evaluating performance of the ESD protection structure. Moreover, multiple ESD structures can be implemented and accurately compared to one another on a test chip as described. The disclosed methods and apparatus are usefull in reduced turn-around time and more accurate evaluation and comparison of ESD protection structures in integrated circuits.

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San Jose, CA, United States of America

Victer K Chan