Taiwan Semiconductor Manufacturing Comp. Ltd.

Amberwave Systems Corporation

Vicky K Yang

Matthew T Currie

Christopher W Leitz

Richard Charles Westhoff

Christopher J Vineis

Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Semiconductor heterostructures having reduced dislocation pile-ups and related methods

Semiconductor heterostructures having reduced dislocation pile-ups

Methods of fabricating semiconductor heterostructures

Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.

Semiconductor structures with structural homogeneity

Semiconductor heterostructures and related methods

Growing community of inventors

Brookline, MA, United States of America

Vicky K Yang