Koninklijke Philips Corporation N.v.

Philips Electronics North America Corporation

Vickram R Vathulya

Tirdad Sowlati

Alok Govil

A space-saving frame member for use in supporting a keyboard adjacent to a monitor. The frame member has an upper end and a lower end, and means for attaching the upper end of the frame member to the monitor such that the lower end of the frame member extends from a lower side of the monitor to support the keyboard. The frame member may be retractable such that when in an extended position, the user can access the keyboard. When the keyboard is no longer in use, the frame member may be retracted such that the keyboard is stored beneath and behind the monitor.

Space-saver design for personal computer keyboard

A capacitor structure having a first level of electrically conductive parallel lines and at least a second level of electrically conductive parallel lines disposed over the lines in the first level, the lines of the first and second levels being arranged in vertical rows. A dielectric layer is disposed between the first and second levels of conductive lines. One or more vias connect the first and second level lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. Electrically opposing nodes form the terminals of the capacitor. The parallel array of vertical capacitor plates are electrically connected to the nodes in an alternating manner so that the plates have alternating electrical polarities.

Interdigitated multilayer capacitor structure for deep sub-micron CMOS

A circuit and method for input side impedance matching of a power amplifier in an electronic device. Specifically, the present invention provides an impedance transformer network that includes a negative resistor in series with a bondwire inductor. The network is placed in parallel with a signal source and synthesizes the source side impedance at the input of the power amplifier. The desired impedance is synthesized by selecting an appropriate value for the negative resistor and setting the reactance of the inductor equal to the capacitance of the electronic device at a required frequency of operation.

Circuit and method for input side impedance matching of a power amplifier in an electronic device

A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.

Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers

A power-on reset circuit input stage includes a current source charging a capacitor from a first power supply voltage to produce a reset signal, and a current shutoff means for shutting off the current source when the reset signal reaches a desired threshold voltage (i.e., when the capacitor is charged up). Beneficially, the current shutoff means comprises a transistor connected between the current source and a second power supply voltage. Advantageously, the transistor is controlled by a feedback voltage that may be the output signal, or a voltage derived from the output signal by a capacitive divider, for example.

Power-on reset circuit with current shut-off and semiconductor device including the same

A MOSFET amplifier includes a pre-amplifier stage and a power amplifier stage. The pre-amplifier is a CMOS inverter having a signal output that is DC connected to the gate of a MOS control transistor of the power amplifier stage. The CMOS inverter includes an NMOS transistor with a source connected through an inductor to ground and a drain to the source of a PMOS transistor. The drain of the PMOS transistor is connected through another inductor to a supply voltage. The gates of the NMOS and PMOS transistors are connected to both receive an input signal of the amplifier.

CMOS radio frequency amplifier with inverter driver

An integrated circuit chip includes a cascode amplifier having a first NMOS transistor with the gate receiving an input signal a source connected to ground through an inductance and a drain connected to the source of a second NMOS transistor. The drain of the second transistor is connected to a supply voltage through another inductance. The gate of the second transistor is connected to a DC bias voltage through a resistor and is connected to a first plate of an on-chip parallel plate capacitor. The other plate of the capacitor is connected to a wirebond pad for connection to a circuit board through a bond wire. The capacitor together with the inductance of the bond wire form a short circuit at the operating voltage of the amplifier.

Compact cascode radio frequency CMOS power amplifier

A capacitor structure, especially for use in deep sub-micron CMOS, having an array of electrically conductive pillars which form the plates of the capacitor. Each of the pillars is formed by electrically conductive lines segments from at least two different conductor levels electrically connected by an electrically conductive via. Dielectric material is disposed between the two conductor levels and the pillars of the array. The pillars are electrically connected to opposing nodes in an alternating manner so that the pillars are electrically interdigitated.

Multilayer pillar array capacitor structure for deep sub-micron CMOS

A capacitor structure having a first and at least a second level of electrically conductive concentric lines of an open-loop configuration. The conductive lines of the at least second level overlie the conductive lines of the first level. A dielectric material is disposed between the first and second levels of conductive lines and between the conductive lines in each of the first and second levels. The conductive lines are electrically connected in an alternating manner to terminals of opposing polarity so that capacitance is generated between adjacent lines in each level and in adjacent levels. The capacitor especially useful in deep sub-micron CMOS.

Multilayered capacitor structure with alternately connected concentric lines for deep sub-micron CMOS

A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.

Growing community of inventors

Croton-on-Hudson, NY, United States of America

Vickram R Vathulya