Intel Corporation

Vicki W Tsai

Inching Chen

Ernest T Tsui

Hooman Honary

Anthony L Chun

A reconfigurable decoder is capable of performing both Viterbi decoding and turbo decoding. The reconfigurable decoder may be repeatedly reconfigured to work with any of a number of different convolutional or turbo coding schemes. In at least one embodiment, the reconfigurable decoder is capable of automatically reconfiguring itself based on a present signal environment about a communication device carrying the decoder.

Reconfigurable Viterbi/turbo decoder

In various embodiments, a processing element (PE) includes a data router adaptor (DRA) and one or more elements that produce function packets. When the DRA receives a function packet, it generates a set of associated router packets. Each of the associated router packets includes a segment of the function packet, and has a router packet data length that is less than or equal to the function packet length. In one embodiment, the router packet data lengths are included in a table, and can be re-configured to alter system performance parameters (e.g., bandwidth usage and/or latency). The DRA sends the set of associated router packets to a router for delivery through a packet-based network. A destination DRA receives the set of associated router packets, and generates a re-assembled function packet from the set of associated router packets. The destination DRA sends the re-assembled function packet to a destination element.

Methods and apparatus for reconfiguring packets to have varying sizes and latencies

Compilation of a design description for a heterogeneous reconfigurable architecture is influenced by user-specified constraints.

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Mountain View, CA, United States of America

Vicki W Tsai