Advanced Micro Devices Corporation

Vibhor Mittal

Deepesh John

Steven Kommrusch

Nur Mohammad Baksh

Michael Q Co

Teja Singh

Samiul Haque Khan

Kedar Karthykeyan

Shravan Lakshman

A method includes generating a functional clock signal, a scan clock signal, and a delayed clock signal based on a control clock signal and a scan enable signal. The method includes precharging or predischarging a differential pair of nodes in a first latch using the delayed clock signal and a voltage on a first power supply node and controlling a second latch using the delayed clock signal. The method includes latching data input by the first latch using the functional clock signal in a functional mode of operation and latching scan data by the first latch using the scan clock signal in a scan mode of operation.

Split-scan sense amplifier flip-flop

An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.

Fine granularity in clock generation

A method for implementing clock dividers includes providing, in response to detecting a voltage drop at a processor core, an input clock signal to a transmission gate multiplexer for selecting between one of two stretch-enable signals. In some embodiments, selecting between the one of two stretch-enable signals includes inputting a set of core clock enable signals into a clock divider circuit, and modifying the set of core clock enable signals to generate the stretch-enable signals. An output clock signal is generated based on the selected stretch-enable signal.

Clock divider device and methods thereof

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Austin, TX, United States of America

Vibhor Mittal