Globalfoundries U.S. Inc.

Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

Vanguard International Semiconductor Singapore Pte. Ltd.

Globalpoundries U.S. Inc.

Vibhor Jain

John Joseph Pekarik

Qizhi Liu

Anthony K Stamper

John J Ellis-Monaghan

Judson Robert Holt

Steven M Shank

Renata A Camillo-Castillo

Siva P Adusumilli

Alexander M Derrickson

Yves T Ngu

Sebastian Theodore Ventrone

Alvin Jose Joseph

Marwan H Khater

Vikas Kumar Kaushal

Johnatan A Kantarovsky

Mark Levy

Hong Yu

Shesh Mani Pandey

Rajendran Krishnasamy

Peng Cheng

James William Adkisson

Yusheng Bian

Shyue Seng Tan

Jagar Singh

David Louis Harame

Xinshu Cai

Ephrem G Gebreselasie

Ajay Raman

Pernell Dongmo

Haiting Wang

Herbert Lei Ho

Hanyi Ding

You Qian

Peter B Gray

Humberto Campanella-Pineda

Robert J Gauthier, Jr

Yung Fu Chong

Natalie Barbara Feilchenfeld

Claude Ortolland

Cameron E Luce

Anupam Dutta

Kien Seen Daniel Chong

Kenneth J Stein

Brendan S Harris

Thomas Kessler

Robert K Leidy

Rakesh Kumar

Viorel C Ontalus

Venkatesh P Gopinath

Zhenyu Hu

Sunil Kumar Singh

Nicholas A Polomoff

Ramsey M Hazbun

James Randall Elliott

Alexander Lee Martin

Rui Tze Toh

Humberto Campanella Pineda

Mankyu Yang

Joan Josep Giner De Haro

Oscar Restrepo

Sarah A McTaggart

Andreas Knorr

Uppili S Raghunathan

Vvss Satyasuresh Choppalli

Mark David Jaffe

Jeffrey Bowman Johnson

Robert Mark Rassel

Steven J Bentley

Alain F Loiseau

Michael Joseph Zierak

Richard Stephen Graf

Rahul Mishra

David C Pritchard

Jianwei Peng

Jack Robert Smith

Ravi Prakash Srivastava

Uzma B Rana

Panglijen Candra

Ezra D B Hall

Richard Francis Taylor, Iii

Santosh Sharma

Ian McCallum-Cook

Janakiraman Viraraghavan

Wei Liang

John J Benoit

Sagar Premnath Karalkar

Blaine Jeffrey Gross

Paula Fisher

Davinder Aggarwal

Andre Sturm

Yan Ding

Abdelsalam Aboketaf

John R Long

Christopher Durcan

Tayel Nesheiwat

V V S S Satyasuresh Choppalli

Jeffrey Johnson

Alain François Loiseau

Yves Ngu

Structures including an optical phase shifter and methods of forming a structure including an optical phase shifter. The structure comprises an optical phase shifter including a waveguide core having a first branch and a second branch laterally spaced from the first branch. The structure further comprises a thermoelectric device including a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit. The first plurality of pillars and the second plurality of pillars disposed adjacent to the first branch of the waveguide core, the first plurality of pillars comprises an n-type semiconductor material, and the second plurality of pillars comprises a p-type semiconductor material.

Optical phase shifter with one or more integrated thermoelectric devices

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a substrate having a top surface, a trench isolation region in the substrate, and a base layer on the top surface of the substrate. The base layer extending across the trench isolation region. A first bipolar junction transistor includes a first collector in the substrate and a first emitter on a first portion of the first base layer. The first portion of the first base layer is positioned between the first collector and the first emitter. A second bipolar junction transistor includes a second collector in the substrate and a second emitter on a second portion of the first base layer. The second portion of the first base layer is positioned between the second collector and the second emitter.

Array arrangements of vertical bipolar junction transistors

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

Bipolar junction transistor arrays

Structures for a junction field-effect transistor and methods of forming a structure for a junction field-effect transistor. The structure comprises a first gate on a top surface of a semiconductor substrate, a second gate beneath the top surface of the semiconductor substrate, and a channel region in the semiconductor substrate. The first gate is positioned between a source and a drain, and the channel region positioned between the first gate and the second gate.

Junction field-effect transistors

The present disclosure relates to semiconductor structures and, more particularly, to an e-fuse with metal fill structures and methods of manufacture. The structure includes: an insulator material; an e-fuse structure on the insulator material; a plurality of heaters on the insulator material and positioned on sides of the e-fuse structure; and conductive fill material within a space between the e-fuse structure and the plurality of heaters.

E-fuse with metal fill

The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

High electron mobility transistor devices having a silicided polysilicon layer

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

Lateral bipolar transistors with gate structure aligned to extrinsic base

Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an emitter, a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section, and an intrinsic base disposed in a second direction between the emitter and the third section of the collector. The structure further comprises a stress layer including a section positioned to overlap with the emitter, the intrinsic base, and the collector. The section of the stress layer is surrounded by a perimeter, and the first and second sections of the collector are each positioned adjacent to the perimeter of the stress layer.

Heterojunction bipolar transistors with a cut stress liner

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Lateral bipolar transistor with gated collector

The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.

Vertical device triggered silicon control rectifier

A semiconductor device includes a first substrate, a second substrate bonded to the first substrate, and at least one thermally conductive structure that extends through a portion of the first substrate and a portion of the second substrate and is vertically aligned with an active region of the first substrate. The at least one thermally conductive structure is electrically insulated from electrically active structures in the semiconductor device. The thermally conductive structure acts as a heat sink to transfer heat from the active region.

Heat sink for face bonded semiconductor device

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Heterojunction bipolar transistor with buried trap rich isolation region

A structure includes a dielectric waveguide, and at least one grating coupler adjacent the dielectric waveguide. Each grating coupler includes a set of parallel optofluidic grating channels oriented orthogonally to the dielectric waveguide. The structure may also include a radiation source operatively coupled to the dielectric waveguide, and an optical receiver such as a photosensor adjacent the grating coupler(s). The structure may be used as part of an optofluidic sensor system for, for example, biochemical applications.

Structure including grating coupler with optofluidic grating channels

The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

Bipolar transistor with stepped emitter

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Essex Junction, VT, United States of America

Vibhor Jain