Cadence Design Systems, Inc.

Vibhor Garg

Krishna Prasad Belkhale

Amit Dhuria

Pawan Kulshreshtha

Hakan Yalcin

Edward J Martinage

An approach is described for a method, system, and product, that includes identification/generation of a synthesized netlist for use in optimization and placement, generation and utilization of multiple uncertainty values for an early clock tree for guiding optimization and placed of circuit elements in a placeopt process that operates on a path by path basis. In some embodiments, the approach further comprises execution of clock tree synthesis, and routing the synthesized clock tree. In some embodiments, uncertainty values are propagated along data paths where each data path is associated with an uncertainty value, and where each path is optimized and placed on a path my path basis in order to meeting timing requirements and one or more design goals.

Method, system, and product for an improved approach to placement and optimization in a physical design flow

According to certain aspects, the present embodiments include techniques for performing a single timing analysis run for a plurality of views representing different modes and/or corners. An embodiment analyzes and maintains relevant timing information that is different for different views, but otherwise maintains the same information for all views. This allows each individual view in a single run to be analyzed in the same manner as separate runs for each separate view, thereby ensuring the same QoR. These and other embodiments provide substantial savings in runtime and memory consumption over other approaches.

Shared timing graph propagation for multi-mode multi-corner static timing analysis

The present disclosure relates to a system for use in electronic circuit design. The system may include a computing device configured to receive, using at least one processor, an electronic design. The at least one processor may be further configured to generate a common path pessimism removal ('cppr') database configured to store one or more cppr tags obtained from an initial timing analysis of at least a portion of the electronic design. The at least one processor may be further configured to apply the one or more cppr tags during a block-level timing analysis.

Systems and methods for calculating common clock path pessimism for hierarchical timing analysis in an electronic design

A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

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Union City, CA, United States of America

Vibhor Garg