Emulex Corporation

Qlogic Corporation

Emulex Corporatioln

Vi Chau

Peter Mark Fiacco

Bradley S Sonksen

Rajendra R Gandhi

Sam S Su

Wayne T Rickard

Dan Tarr

Stuart B Berman

Kuangfu David Chu

Jennifer Sullivan

Manickam Ananthan

Methods and systems for a device interfacing with a computing system are provided. The device is configured to send an input/output status block (IOSB) and an interrupt message to the processor of a computing system interfacing upon completion of an operation. The device generates the interrupt message while the IOSB is waiting to be transmitted; and transmits the IOSB to the processor, followed by the interrupt message, using a same data path for both the IOSB and the interrupt message. Furthermore, the device is configured to detect a request from the processor of the computing system interfacing to clear an interrupt status maintained by the device at a hardware location; send a message to the processor to de-assert the interrupt status and in parallel, clear the hardware location to clear the interrupt status such that the computing system can transfer information to the device for a next operation.

Method and system for communication between a computing device and a peripheral device

An adapter having a plurality of functions and a plurality of ports, in which the mapping between functions and ports is configurable. In certain embodiments, device memory can be programmed with a desired mapping scheme that overrides a default mapping scheme for the adapter. In certain embodiments, device memory can be reprogrammed with a different desired mapping to enable the adapter to dynamically respond to system conditions.

System and method for mapping functions to and from network devices using configuration compatible with an adapter by remapping plurality of logical ports of adapter

Method and system for protecting data in a PCI-Express device is provided. The method includes adding error correction code (ECC) to every byte of data that enters a PCI-Express Transaction Handler ('PTH') Module and is destined for a host system memory or destined to another device, before the data is aligned within the PTH module; verifying the ECC code for every byte of the data before the data leaves the PTH module; and generating the ECC code for a data block size, wherein the data block size depends on the destination of the data.

Byte level protection in PCI-Express devices

A 'virtual FIFO' system for use in buffering data between transacting buses that transfer data at different rates includes a memory device and a controller that partitions the memory device into multiple regions, each of which is configured to operate as a distinct data buffer.

Buffering data that flows between buses operating at different

A system is configured to provide an efficient management or control of a buffer memory system. The system can also be used to transmit data between communicating components of a computer system. A first-in-first-out memory stores a list of buffer pointers, and control logic returns buffer pointers from the transmit registers, and moves buffer pointers to the bottom of the FIFO memory.

Efficient transmission buffer management system

A partitioned memory is divided into a number of large buffers, and one or more of the large buffers is divided to create an equal number of small buffers. Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

Memory buffer system using a single pointer to reference multiple

An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.

Elastic bus interface data buffer

A method and apparatus for linking two independent caches which have related information stored therein. Each unit of information stored in a first cache memory is associated with one unit of information stored in the second cache memory. Each unit of information stored in the first cache memory includes a pointer or index to the associated information unit in the second cache memory. Each information unit stored in the second cache is only stored once, regardless of the number of units in the first cache that are associated with a particular unit within the second cache. Therefore, even if more than one unit of information within the first cache memory is associated with the same unit of information within the second cache memory, that unit of information stored in the second cache memory is only stored once.

Linked caches memory for storing units of information

A method and apparatus for establishing a large number of EDTOV timers, each determining when an event has failed to occur on an exchange of a communications protocol. Values for each timer are maintained as a timer array. The entire timer array is read at regular scan intervals by a state machine and decremented by four associated hardware decrementers, four timers at one time. A Scan Interval variable determines the scan interval. The present invention is capable of scan intervals of up to 100 ns. Active time values are read, checked for zero, decremented preferably by one, and written back to the timer array. If a timer is detected as having timed out (equal to zero), then a value which identifies the exchange associated with that timer is logged into a time-out FIFO and 'FF'h is written back into the timer. At the heart of the invention is the efficient use of dedicated hardware to decrement or otherwise alter the values of each timer as appropriate, and the use of a dedicated state machine to read values for each timer, provide the value to the hardware, and then load the new value of each timer back into memory.

Computer control device for managing a timer array

A system and method for burst broadcasting data from a master device to multiple target devices over a peripheral component interconnect (PCI) bus. Initially, an initiator device in the system captures control of the bus. The initiator device inspects an internal coherency flag. The initiator device releases the bus if its coherency flag is set (if the initiator device is not in the middle of a previously commenced burst broadcast, in which case it keeps control of the bus). The initiator device then sets the coherency flag in each of the other devices, and concurrently sets it own coherency flag. Once all the coherency flags are set, the initiator device broadcasts a block of data on the bus to each of the other devices simultaneously. Once the burst-broadcast is complete, the coherency flags in the initiator device and each of the other devices are concurrently reset by the initiator device. The invention augments an existing bus technology by adding a new mode of operation.

Growing community of inventors

Laguna Niguel, CA, United States of America

Vi Chau