Interuniversitair Microelektronica Centrum (imec)

Imec

Vesselin K Vassilev

Guido V Groeseneken

Steven Thijs

Vincent De Heyn

Natarajan Mahadeva Iyer

Tom Daenen

A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline. The method may use a rectangular pulse testing set-up, also known as transmission line measurement set-up, with a single loadline characteristic to determine a portion or the complete ESD characteristic of the device-under test.

Method of determining current-voltage characteristics of a device

The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.

Device for electrostatic discharge protection

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Leuven, Belgium

Vesselin K Vassilev