Broadcom Corporation

Veronica Alarcon

Mark Norman Fullerton

Walid Nabhane

Love Kothari

Chih-Tsung Hsieh

Hao-zheng Lee

Ronak Subhas Patel

Mark David Rutherford

Amar Guettaf

Kerry Thompson

Arun Palaniappan

Zhongmin Zhang

Ajmal A Godil

Chun-Nan Ke

John Russell Platenak

Rajesh Rajan

Aspects of enhanced recovery mechanisms are described. A predetermined operating parameter for a power rail is set at the outset of system start. Afterwards, a processor is released to start with a power management circuit. In turn, the power management circuit receives a default operating parameter for the power rail from the processor, and stores the default operating parameter. The power management circuit also receives a runtime operating parameter for the power rail from the processor and modifies the operating parameter for the power rail according to the runtime operating parameter. If an error condition in the processor is encountered, the power management circuit may modify the operating parameter for the power rail according to the default operating parameter in response to a reset control signal from the processor. Use of the default operating parameter for the power rail may assist the processor to recover from the error condition.

Enhanced recovery mechanisms

A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor.

Clock domain crossing serial interface

Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner.

Power mode register reduction and power rail bring up enhancement

Aspects of dynamic power profiling are described herein. In various embodiments, a current sense operating mode is set for a current sense circuit, and the current sense circuit is enabled for operation. The current sense circuit senses an amount of current supplied by at least one of a plurality of power rails based on the current sense operating mode. The current sense circuit also accumulates and stores a value of the amount of current over a period of time. In certain aspects, a system controller averages the value of the amount of current based on the period of time. The current sense circuit may be configured to operate in various modes of operation including single or scan rail modes of operation, and the average of the value of the amount of current may be evaluated based on the modes of operation of the current sense circuit and/or the system.

Dynamic power profiling

An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.

Electronics device capable of efficient communication between components with asyncronous clocks

Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.

Clock domain crossing serial interface, direct latching, and response codes

An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit. Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test mode

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San Jose, CA, United States of America

Veronica Alarcon