Pmc-sierra, Inc.

Vernon Robert Little

Charles Kevin Huscroft

Brian D Gerson

David Walden Wong

Graham B Smith

Barry Benjamin Hagglund

Heng Liao

Thomas Alexander

Stacy W Nichols

Steven F Lang

Stephen Julien Dabecki

John Richard Bradshaw

Kevin Huscroft

Salman Ghufran

Yuming Tao

A method and apparatus for building a packet grooming and aggregation engine is disclosed. The grooming and aggregation engine can be applied to the network for providing flexible aggregation and service multiplexing functions. A method and apparatus achieves the intended function that is easy to implement and easy for the network operator to manage, yet provides enough flexibility to mix and match various services at the edge node of the network. One specific embodiment of the patent is an Ethernet over SONET mapping system where user traffic is aggregated and groomed into SONET transport virtual concatenation channels.

Method and apparatus for packet grooming and aggregation

Gridded I/O pads for flip-chip packages in which a coaxial-like solder bump pad configuration is used in which the I/O pads closest to the signal or bump pad are power or ground pads. The ground pads surrounding the signal pad form a coaxial-like pad configuration for impedance matching at the transition from die to package substrate. The ground pads surrounding the signal pad may be connected by a metal trace to form a ground pad ring. The invention employs conductor-backed ground coplanar waveguides (GCPW), which match impedance at connections between I/O cells and signal pads to enhance signal transmission, avoid reflection and leakage, and provide superior electromagnetic shielding. The present invention also supports high quantities of I/Os for a given die size, and supports flexible power and ground placement.

High speed I/O pad and pad/cell interconnection for flip chips

A method of communicating data frames between nodes in a network comprised of one or more end system nodes where each end system node has a unidirectional ingress port and a unidirectional egress port. The method comprises transmitting a data frame from an egress port of one end system node to the ingress port of another end system node, the receiving end system node then determining whether it is the final destination for the data frame. If the receiving end system node is the final destination of the data frame, the receiving end system node absorbs the message. If not, the receiving end system node buffers and then retransmits the data frame through its own egress port. The method provides scalability, low cost, distributed pipeline scheduling, maximum complexity of the network fabric, and maximum speed.

Communication method for packet switching systems

A method of providing broadband communication services to a subscriber comprised of providing first broadband services from a central office via an ATM link to a neighborhood pedestal system, providing time division multiplex (TDM) services including voice communication services from the central office via a TDM link to the neighborhood pedestal system, providing a SONET-ATM communication link from the neighborhood pedestal system over two unshielded pair of twisted wires to a user-to-network interface (UNI) at a subscriber location, and providing ATM services over the SONET-ATM communication link and providing integrated services digital network (ISDN) or voice services within a SONET-ATM data frame using timing of the SONET-ATM communication link, to the UNI, whereby ATM, ISDN and voice services are provided between the neighborhood pedestal system and the subscriber location over the unshielded wires.

Low cost ISDN/pots service using ATM

A user network interface device for interfacing between synchronous optical network (SONET)/synchronous digital hierarchy (SDH) which is characterized by a continuous stream of frames of data and an asynchronous transfer mode (ATM) characterized by a non-continuous stream of cells of data. The user network interface device includes an integral phase lock loop circuit to recover clock and data from an encoded incoming stream of data. In another embodiment, the network interface device synthesizes a high speed transmit clock from a low frequency reference source.

Integrated user network interface device for interfacing between a sonet network and an ATM network

According to the invention there is provided a method of signal coding that permits high speed data transmission over multiple pairs of UTP-5 cable from a transmission end to a receiving end which includes, at the transmission end, separating an incoming frame of data into a plurality of byte streams with a predefined sequence of bytes assigned to each of the streams, encoding every 2 bits of data in each stream into one of 4 logical voltage levels forming a symbol or quat thereby reducing the symbol or baud rate by 50% and inserting an escape sequence into one or more of the streams consisting of a sequence of zero's followed by a control code to indicate a transition from one state to another. At a receiving end, the method further includes reading the escape sequence and decoding the signals in accordance with the code contained in the escape sequence.

Line coding technique for efficient transmission and delineation of

An ATM network interface comprising a physical layer interface having transmit and receive line interfaces, transmit and receive framers and overhead processors coupled to respective ones of the transmit and receive line interfaces and transmit and receive cell processors coupled to respective ones of transmit and receive framers and overhead processors. The interface further includes a segmentation and reassembly interface coupled to the physical layer interface having transmit and receive ATM and adaptation layer processors coupled to respective ones of the transmit and receive ATM cell processors and a transmit ATM Traffic Shaper coupled to said Transmit ATM and Adaptation Layer Processor, and a coupler to couple the segmentation and reassembly interface to a PCI bus. By incorporating the SAR unit on the same monolithic device as the remainder of the interface, one is able to eliminate the need for expensive external static RAM or SRAM for connection context memory.

Combination local ATM segmentation and reassembly and physical layer

A method of interfacing between a non-continuous stream of cells of data and a continuous stream of frames of data, which includes transforming an incoming non-continuous cell stream into a continuous transmitted stream by inserting idle or non-assigned cells into the data stream during idle periods. The cells in the continuous stream are then mapped sequentially and contiguously onto the payload portions of frames. The frames are then transmitted synchronously.

Integrated user network interface device

A design protection circuit for a logic circuit comprised of a counter for receiving clock pulses with the logic circuit and apparatus for resetting the logic circuit upon the counter counting a predetermined number of clock pulses, the predetermined number being higher than a highest number of clock pulses required by the logic circuit for carrying out a simulated logical function.

Method for protecting an ASIC by resetting it after a predetermined time

For use in a transmission system in which an input data stream is transmitted in plural data streams each at a fraction of the input data stream rate and plural clock stream pairs each at the fraction of the input data clock rate, a receiver, comprised of apparatus for receiving the plural data streams, apparatus for determining frame timing differences between frame signals contained in each of the received plural data streams, apparatus for varying the timing of one received data stream relates to another, whereby their relative timing is adjusted, apparatus for combining the timing adjusted plural data streams into an output data stream having a similar data stream rate as the input data stream, apparatus for recovering a clock from one of the plural data streams, and for generating an output clock signal therefrom at the input data clock rate, and apparatus for aligning the output data stream with the output clock signal, whereby an output data stream and an output clock signal are provided having similar data rates as the input data stream and clock rates.

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Belcarra, Canada

Vernon Robert Little