Motorola Corporation

Vernon L Brown

Gregory Joseph Dunn

Lawrence E Lach

Yaroslaw A Magera

James E Mitzlaff

Jovica Savic

Scott David Beutler

Min-Xian M Zhang

Mike M Albert

Robert L Benenati

Yaroslaw Antin Magera

Lola Conway

Julia S Johnson

George E White

Joseph Desjardins

A process for forming a resistor whose dimensions can be accurately determined by a photoimaging process, thereby yielding a resistor whose size and resistance value render the resistor a viable alternative to discrete chip resistors. The resistor is formed of a photoimageable resistive thick-film material that enables the dimensions of a resistor to be determined directly by photodefinition instead of conventional screen printing. Electrically-conductive terminations are provided that determine the electrical length of the resistor. The terminations may be formed prior to depositing the resistive layer, or after the resistive layer has been photoimaged and developed. If the latter approach is used, the terminations may be formed by depositing a photoimageable layer on the resistor, photoimaging and developing the photoimageable layer so as to form openings that expose regions of the resistor, and then plating, e.g., electrolessly plating, a conductive material on the exposed regions of the resistor to form terminations that overlie the resistor. Alternatively, by formulating the photoimageable layer to be plateable, a second photoimageable layer can be deposited on the plateable photoimageable layer prior to plating the conductive material, and then photoimaged and developed to form openings that expose regions of the plateable photoimageable layer that are adjacent the regions of the resistor exposed by the openings in the plateable photoimageable layer. Thereafter, the conductive material can be plated on the regions of the resistor and the plateable photoimageable layer exposed by the openings to yield terminations and connectors to the resistor.

Method for forming a thick-film resistor

A method for attaching a flip chip or other microelectronic device to a circuit board or other substrate. The method entails the forming of recesses having precise volumes above and surrounding each terminal pad so as to enable the deposition on each pad of a controlled volume of conductive material, such that reduced spacing between terminals can be enabled. If a conductive adhesive is used as the conductive material, the method drastically reduces the likelihood that an inadequate amount of adhesive will be deposited, while excess adhesive can be accommodated without causing shorting between adjacent terminals. If flip chip attachment is achieved with a solder composition, the method eliminates the prior art requirement for circuit board terminal bumping and bump flattening.

Method for attaching an electronic device

A thick-film resistor and a process for forming the resistor to have accurate dimensions, thereby yielding a precise resistance value. The resistor generally includes an electrically resistive layer and a pair of terminals, a first of which is surrounded by the second terminal, so as to form a region therebetween that surrounds the first terminal and separates the first and second terminals. The terminals are preferably concentric, with the second terminal and the region therebetween being annular-shaped. The resistive layer electrically connects the first and second terminals to complete the resistor. Each of the terminals has a surface that is substantially parallel to an upper and/or lower surface of the resistive layer and contacts the resistive layer. The surfaces of the terminals may be embedded in the resistive layer by printing the resistive material over the terminals, or may contact the upper or lower surface of the resistive layer by locating the terminals above or below the resistive layer. In each of these embodiments, the terminals are not limited to having edge-to-edge contact with the resistive layer, such that the interfacial resistance therebetween is minimized.

Thick-film resistor having concentric terminals and method therefor

A process for forming a double-sided or multi-layered circuit structure entailing the use of a fill material that forms a conductive connection between the layers of the circuit structure and photodefinable resins that form permanent dielectric layers and plateable surfaces of the circuit structure. The method includes forming a through-hole in a substrate, and then filling the through-hole with the fill material containing a metal that is catalytic to electroless copper. The fill material forms an electrical connection having oppositely-disposed connection surfaces that are coextensive with opposite surfaces of the substrate. A first photodefinable dielectric layer is then formed on each surface of the substrate, including the connection surfaces, and openings are photoimaged and developed in the dielectric layers to expose a portion of each connection surface. A second dielectric layer is then formed over each of the first dielectric layers and the exposed portions of the connection surfaces, with an opening being formed in each of the second dielectric layers to re-expose the portions of the connection surfaces and contiguous surface portions of the first dielectric layers. The exposed surface portions of the first dielectric layers and the exposed portions of the connection surfaces are then electrolessly plated with copper to form conductor traces on each side of the substrate. As a result, the traces electrically contact the connection surfaces, such that traces on opposite sides of the circuit structure are interconnected with the connection formed by the fill material in the through-hole.

Method for forming a high-density circuit structure with interlayer

A process for metallizing an integrated circuit chip to form an interconnecting pattern for the chip's input/output terminals, wherein the process can be performed while the chip is still a part of the wafer on which it is fabricated and before separation into individual chips. The invention uses photodefinable resins as masks that form permanent dielectric layers of a multilayer structure with which interconnecting paths and terminals are defined on the surface of the chip. The process further employs conversion techniques that enable the interconnecting paths to be formed from metals other than aluminum, such that the electrical performance of the chip is enhanced. The use of the photodefinable resins renders the process of this invention conducive to inline processing techniques, thereby reducing processing costs while promoting high throughput and short cycle times. The process of this invention also enables the interconnecting paths to be readily customized for adaption to changing configuration requirements at the next assembly level, while also promoting greater dimensional precision of bumps formed at the terminals.

Metallization and termination process for an integrated circuit chip

A masking method employing a photodefinable resin as a permanent dielectric mask, in which the resin contains a catalytic filler that when activated enables direct electroless plating of the resin. The resin serves to simplify selective electroplating of isolated surface features such as metal pads, while also improving the topology of the external surface of the circuit board, particularly when small metal pads require a controlled volume of a reflowable metal. The resin is preferably photodefined to eliminate recessed areas around the metal pads, thereby promoting definition of the metal features, and yielding a nearly planar surface. Additional features that can be provided with the method include external conductive ground planes and electromagnetic shield layers within a multilayer circuit board. The masking method can be advantageously used with both reflowable metals and metal alloys, such as tin/lead, and nonreflowable metals and metal alloys, such as gold, palladium and platinum.

Solder mask system

A method for metallizing selected areas of a two dielectric layered sequentially processed circuit board (100) involves exposing the resin A (204) by photo-definition. The resin A (204) contains 10% or less, by weight Cu.sub.2 O particles (300) mixed uniformly throughout the resin. The circuit board (100) is sprayed with a reduction solution to form catalytic islands (301) predominately of Cu.sup.0 or CuH. The circuit board (100) is then electrolessly plated to form conductors, pads or vias, where the resin A (204) has been exposed. The reduction solution includes a primary reducing agent, a secondary reducing agent and a capturing agent. The reduction solution preferably has a pH of 10 or greater. The primary reducing agent is preferably a borohydride. The secondary reducing agent is preferably an iodide and the capturing agent is a chelating agent preferably EDTA.

Method and reduction solution for metallizing a surface

A dielectric layered sequentially processed circuit board is disclosed. A first photodefinable resin containing an electroless plating catalyst is disposed on a substrate and portions of the substrate are exposed through the first resin. A second photodefinable resin absent the electroless plating catalyst is disposed on the first resin, and portions coincident with the exposed portions of the substrate as well as portions of the first resin are exposed through the second resin. A conductive material is deposited on the exposed portions of the substrate and the exposed portions of the first resin.

Dielectric layered sequentially processed circuit board

A semiconductor chip carrier (SCC) comprising means for physical orientation and attachment to a substrate which is independent of means for coupling electrical signals to the substrate, thereby alleviating many of the constraints often placed on the substrate and/or electrical coupling system.

Semiconductor chip carrier

A unique process metallizes a substrate surface using a reducing agent including a borohydride to reduce, in a starved reaction, metal oxide particles (300) substantially uniformly distributed and at a controlled concentration in a particle-filled resin (204) to produce catalytic island areas (301). The catalytic island areas (301) formed have a surface resistivity greater than 10.sup.6 ohms per square. These catalytic island areas (301) are then electrolessly metallized to a predetermined thickness, such that adjacent catalytic island areas (301) are interconnected and form metallic features, such as pads, vias (213), and conductors (210, 211 and 212). The starved reaction limits the reduction of metal oxide particles (300) to catalytic island areas (301) and prevents migration of reduced metal beyond each of the exposed surfaces of particle-filled resin (204) which are to be metallized.

Process for metallizing substrates using starved-reaction metal-oxide

A unique housing (104) of a portable radio transceiver (100) is described that takes advantage of the heat sinking, electrical shielding and structural characteristics of a battery. The unique electronic circuitry housing (104) includes a battery as a structural element thereof. In one illustrated housing (104), a stick battery (210) is attached to the side of a transmitter printed circuit panel (213). A logic printed circuit panel (212) and a receiver printed circuit panel (214) are positioned above and below the transmitter printed circuit panel (213), respectively, and are held together by interlocking side rails (206,207). The electronic circuitry housing of the present invention may be advantageously utilized in a variety of applications where electronic circuitry is operated from a battery.

Portable radio transceiver housing structurally supported by a battery

A unique housing (104 and 600) of a portable radio transceiver (100) is described that takes advantage of the heat sinking, electrical shielding and structural characteristics of a battery. The unique electronic circuitry housing (104 and 600) includes a battery as a structural element thereof. In one illustrated housing (104), a stick battery (210) is attached to the side of a transmitter printed circuit panel (213). A logic printed circuit panel (212) and a receiver printed circuit panel (214) are positioned above and below the transmitter printed circuit panel (213), respectively, and are held together by interlocking side rails (206,207). In a second illustrated housing (600), a flat battery (602) is attached to the sides of a first U-shaped printed circuit panel (604). A second U-shaped printed circuit panel (606) is positioned between the battery and the first panel (604). Heat dissipated by the electrical components on the second panel (606) is conducted away by the flat battery (602). The electronic circuitry housing of the present invention may be advantageously utilized in a variety of applications where electronic circuitry is operated from a battery.

Portable radio transceiver housing structurally supported by battery

A leadless chip carrier for RF power transistors or the like is disclosed which includes a body of insulating material having two major surfaces and side walls joining the major surfaces. In a first embodiment, a pattern of conductive pads is deposited on one major surface. A pattern of conductive contact areas is deposited on the other major surface and distributed interconnecting portions of conductive material are deposited to connect the pads to the respective contact areas. In a second embodiment, larger pads and contact areas are provided on a beryllia substrate to provide a leadless chip carrier for RF transistors capable of handling 8 watts. In a third embodiment, a single slot is made conductive to provide the distributed interconnecting portion for one terminal, while in a fourth embodiment, the slot is changed to a plurality of small, tungsten-filled through holes to provide a virtually hermetically sealed leadless chip carrier for RF power transistors.

Leadless chip carrier for RF power transistors or the like

A unique housing (104) or a portable radio transceiver (100) is described that includes unique metal printed circuit panels providing for grounding and heat sinking of electrical components and circuitry thereon, and a battery as a structural element thereof. In one illustrated housing (104), three printed circuit panels (212, 213 and 214) and a stick battery (210) are held together by interlocking side rails (206,207). The unique printed circuit panels (212, 213, and 214) include mesas (422) that protrude through corresponding holes in the dielectric and circuitry layers (404 and 406) laminated on the panel. The mesas (422) are preferably soldered to the circuitry layer or electrical components thereon. The shape and size of the mesas (422) can be varied to provide the desired grounding and/or heat sinking. The unique metal printed circuit panel of the present invention may be advantageously utilized in a variety of applications including battery-operated radio transceivers, such as, for example, cellular radiotelephone systems and trunked radio systems.

Growing community of inventors

Barrington, IL, United States of America

Vernon L Brown