Ncr Corporation

Unitrends, Inc.

Intel Corporation

Vernon Keith Boland

John H Waters

Kevin R Brasche

Kenneth A Smith

Alberto Gonzalez Martos

Richard R Barton

Peter Washington

Steven R McDowell

Ernest C Coskrey, Iv

Elizabeth Campbell

Robert N Josephson, Ii

Harold B Raynor

A method and system for the backup and recovery of a converged infrastructure computer system are provided with the ability to determine if the backup meets requirements of a disaster recovery plan. The method and system provide backup and recovery of the data and applications including backup and recovery of the configuration and mapping information of the converged infrastructure computer system. The backups are periodically tested to determine if they meet predetermined metrics that are specified in the disaster recovery plan.

Disaster recovery validation

An illustrative method for validating integrity of a source server backup includes receiving, at a recovery server, data indicating a state of a data storage unit associated with a source server, creating a virtual hard drive image from the received data, and storing, in memory of the recovery server, the created virtual hard drive image. The method also includes booting a virtual machine using the stored hard drive image and mounting a second drive image to the virtual machine including tools facilitating access to an operating system running on the virtual machine by an application running on the recovery server. The tools are prevented from being installed in an operating system running on the source server. The method further includes automatically detecting, by a recovery application running on the virtual machine, that the drive includes the tools, automatically installing, by the recovery application and without user intervention, the tools in the operating system running on the virtual machine, and controlling, by the application running on the recovery server, applications running on the virtual machine.

Automated testing of physical servers using a virtual machine

Consent-based application programming interfaces (APIs) are used to provide privacy access controls to operational systems for business services accomplished particularly in an electronic and/or networked environment. An API implementation device or host provides a link between a channel application, configured to provide an interface with a customer, and privacy data as used by operational applications and obtained from databases such as data warehouses. The privacy APIs provide per-customer choice/consent to obtaining and/or retrieval of privacy information/data and per-customer access thereto. In one form, the privacy APIs are used in business initiated self service applications wherein an activity or event triggers business to customer initiation.

Architecture and method for operational privacy in business services

A method of allocating and distributing processes to network resources. The amount of network resources is determined for each process or groups of processes to be executed on the computer network. A minimum source allocation is provided for one or more of the processes. Each of the network resources is monitored for resource use. If necessary, a resource allocator redistributes network resources in accordance with the minimum resource allocation.

Method and apparatus for allocating network resources and changing the allocation based on dynamic workload changes

A computer system operable to provide nodes of a cluster with a quorum resource includes a network interface controller, a mass storage device, a processor, and memory. The network interface controller is operable to send messages to the nodes via a network and receive messages from the nodes via the network. The mass storage device includes storage that is used to implement the quorum resource and that is accessible by the nodes via the network interface controller. The processor is operably coupled to the network interface controller and the mass storage device. The memory is operably coupled to the processor and includes instructions, which when executed by the processor, cause the processor to process a first message requesting ownership of the quorum resource that is received from a first node of the cluster via the network interface controller. Furthermore, the instructions cause the processor to determine whether the first node already owns the quorum resource in response to receiving the first message. Moreover, the instructions cause the processor to determine whether a second message requesting ownership of the quorum resource is received from a second node of the cluster within a predetermined time period of receiving the first message it the first node does not already own the quorum resource. The instructions cause the processor to grant ownership of the quorum resource to the first node if the second message is not received within the predetermined time period.

Quorum arbitrator for a high availability system

An improved affinity scheduling system for assigning processes to processors within a multiprocessor computer system which includes a plurality of processors and cache memories associated with each processor. The affinity scheduler affinitizes processes to processors so that processes which frequently modify the same data are affined to the same local processor&mdash;the processor whose cache memory includes the data being modified by the processes. The scheduler monitors the scheduling and execution of processes to identify processes which frequently modify data residing in the cache memory of a non-local processor. When a process is identified which requires access to data residing in the cache memory of a non-local processor with greater frequency than the process requires access to data residing in the cache memory of its affined local processor, the affinity of the process is changed to the non-local processor.

Affinity scheduling of data within multi-processor computer systems

A memory management system and method that determines which page or pages in cache memory are likely to be accessed again in the near future by another transaction and designates those pages for recycling so that the pages are maintained in the cache memory for a longer period of time. That is, pages designated for recycling are maintained in the cache, while pages that are not are first replaced. According to the present application, pages in the cache that are likely to be accessed in the near future are those that are accessed by two or more different transactions during their normal residence in the cache.

Method for holding cache pages that are not invalidated within normal time duration for a second access or that are likely to be accessed again soon

An improved affinity process scheduling method for a multiprocessor computer system, wherein a process previously executed on a processor within the computer system is affined to the processor on which it previously executed, and will be scheduled for execution by the affined processor during subsequent requests for execution of the affined process. The improved affinity process scheduling method monitors the length of time the affined process resides on the system run queue awaiting execution by its affined processor; and schedules the affined process for execution with another available processor when the length of time the affined process has been waiting for execution exceeds a predetermined 'steal-age' threshold. The improved affinity process scheduling method also monitors the processing load borne by the affined processor, determines therefrom a headroom parameter for the affined processor, the headroom parameter indicating the remaining load capacity of the affined processor; and schedules the affined process for execution with another available processor when the headroom of the affined processor is less than a predetermined 'low-headroom' threshold.

Method for load balancing a per processor affinity scheduler wherein

A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.

Method and apparatus for enabling physical memory larger than

A method for assigning processes to processors within a multi-processor computer system employing a sleep/wakeup facility whereby a first process requiring information from a second process is placed into a 'sleep' state by said computer system until said second process is able to provide said required information, said first process thereupon being awakened by said computer system so that said first process may continue processing with the required information. The method comprising the steps of identifying a pair of processes which frequently exchange wakeup requests, and assigning the processes within the pair of processes to the same processor within the multi-processor computer system for execution. To identify frequently communicating processes, the method of the present invention maintains a record of each 'wakeup' request issued by the computer system, the record including: an identification of the process on whose behalf said wakeup request is issued; and an identification of the process to which said wakeup request is issued. The records are periodically examined to determine a count of the number of wakeup requests between pairs of processors. Should the number of wakeup requests between two processors exceed a predetermined threshold, those two processors are assigned to the same processor within the multi-processor computer system for execution.

Method for improving the execution efficiency of frequently

A method and apparatus for providing coherency for cache data in a multiple processor system with the processors distributed among multiple independent data paths. The apparatus includes a set of cache monitors, sometimes called snoopers, associated with each cache memory. There are the same number of monitors as there are independent data paths. Thus, each cache stores cache tags that correspond to its currently encached data into each of the monitors of the set associated therewith. Thus, each cache has an monitor associated therewith which monitors each of the multiple paths for an operation at an address that corresponds to data stored in its cache. If such an access is detected by one of the set of monitors, the monitor notifies its cache so that appropriate action will be taken to ensure cache data coherency.

Growing community of inventors

Lexington, SC, United States of America

Vernon Keith Boland